Abstract: On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.

Abstract: The present invention relates to an exponential function generator which is realized with only CMOS element without BJT element, not limited by the physical properties of the element or a square circuit, and not complicated in its configuration, and a variable gain amplifier using the same. The exponential function generator includes a voltage-current converter, 1st to nth curve generators for mirroring the current from the voltage-current converter, outputting a current adjusted according to a predetermined ratio, and an output end for outputting the sum of the current from the 1st to nth curve generators. The exponential current generator is configured to generate the current exponentially adjusted according to the control voltage.

Abstract: There is provided a frequency synthesizer including a multi-band voltage controlled oscillator having a plurality of voltage controlled oscillating cores outputting oscillation frequencies having different bands according to an input control voltage. Each of the voltage controlled oscillating cores outputs a frequency band divided into a plurality of bands, and the voltage controlled oscillating core operates by each of the divided bands, and one of the voltage controlled oscillating cores operates in one of the bands according to the control voltage. The frequency synthesizer further includes a comparator unit and an oscillation band-determining unit. The comparator unit compares the control voltage with a pre-set reference voltage range. The oscillation band-determining unit changes the band where the voltage controlled oscillating core operates into another one of the bands when the control voltage is out of the pre-set reference voltage range.

Abstract: An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.

Abstract: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

Abstract: There is provided a bias current generating apparatus capable of providing a bias current where a characteristic change is compensated, to one of an analog circuit and RF circuit where various characteristic changes occur according to a temperature, by generating bias currents having a plurality of temperature coefficients.

Abstract: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

Abstract: A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable test and a wafer burn-in test to generate a reset signal and a control signal generating block for receiving a plurality of input signals activated in a wafer burn-in test to generate a plurality of test control signals in response to the reset signal and a programmable test signal activated in a programmable stress test.

Abstract: A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

Abstract: The present invention relate to a wideband frequency generating apparatus using a frequency dividing method of dividing a frequency signal of a voltage control oscillator to expand a frequency generating range.

Abstract: In a quadrature voltage controlled oscillator, a first oscillator includes a first resonant circuit for generating a preset first resonant frequency and a first pair of cross-coupled transistors for supplying energy to the first resonant frequency to generate first and second signals having a phase difference of 180°. A second oscillator includes a second resonant circuit for generating a preset second resonant frequency and a second pair of cross-coupled transistors for generating third and fourth signals for supplying energy to the second resonant frequency having a phase difference of 180°. A first current source is connected between a first common node of the first cross-coupled transistor pair and a ground. A second current source is connected between a second common node of the second cross-coupled transistor pair and the ground. A differential load is connected between a third common node of the first and second current sources and the ground.

Abstract: An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.

Abstract: A test mode controller is capable of reducing a chip area and unnecessary current consumption by integrally constructing latch units of the two test circuits. The test mode controller includes a test control block for determining a test mode between a programmable test and a wafer burn-in test to generate a reset signal and a control signal generating block for receiving a plurality of input signals activated in a wafer burn-in test to generate a plurality of test control signals in response to the reset signal and a programmable test signal activated in a programmable stress test.

Abstract: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

Abstract: A frequency conversion apparatus having a mixer eliminates phase miss-matching between two intermediate frequency (IF) signals having the same frequency and a 90 degree difference in phase. The frequency conversion apparatus for compensating for phase mismatching of first and second IF signal in response to an RF input signal transmitted through an RF input terminal includes a quadrature signal generator (QSG) outputting first and second oscillating frequency signals having a 90 degre difference in phase, a first mixer mixing the RF input signal with a first resultant frequency signal having a first resultant phase and generated from the first oscillating frequency signal and an inverted signal of the second oscillating frequency signal, and a second mixer mixing the RF signal with a second resultant frequency signal having a second resultant phase and generated from the second oscillating frequency signal and an inverted signal of the first second oscillating frequency signal.

Abstract: A linear channel select filter for an Intermediate Frequency selector of a satellite broadcasting tuner, linearly changes a desired frequency by adjusting an output current, and includes: a transconductance (GM) current cell controller for determining a control voltage according to a select signal, generating the output current according to an differential input voltage, linearly controlling the output current according to the control voltage, and providing a linearly variable resistance according to the linearly controlled output current, and a capacitor circuit coupled to the GM cell controller to provide a capacitance to generate a cutoff frequency voltage according to the output current and the variable resistance. An occupying area and a size of the filter are reduced.

Abstract: A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

Abstract: Disclosed is a quadrature signal generator for generating an in-phase signal and a quadrature-phase signal, which is capable of generating a quadrature signal having the same frequency as a differential oscillating frequency, using a feedback control system.

Abstract: The present invention relates to a variable oscillation frequency resonance circuit and voltage controlled oscillator using the same, which includes an inductance element, frequency varying means, and oscillation band varying means. The oscillation band varying means is provided with one or more capacitance element pairs and one or more differential switching element pairs each being arranged between capacitance elements of each of the capacitance element pairs, with differential switching elements of each of the differential switching element pairs being arranged in parallel with each other, to allow a corresponding capacitance element pair to be connected to the inductance element in response to second control signals.

Abstract: The present invention relates to a variable oscillation frequency resonance circuit and voltage controlled oscillator using the same, which includes an inductance element, frequency varying means, and oscillation band varying means. The oscillation band varying means is provided with one or more capacitance element pairs and one or more differential switching element pairs each being arranged between capacitance elements of each of the capacitance element pairs, with differential switching elements of each of the differential switching element pairs being arranged in parallel with each other, to allow a corresponding capacitance element pair to be connected to the inductance element in response to second control signals.