Abstract: The present invention provides an olivine-type positive active material precursor for a lithium battery that includes MXO4-zBz (wherein M is one element selected from the group consisting of Fe, Ni, Co, Mn, Cr, Zr, Nb, Cu, V, Ti, Zn, Al, Ga, Mg, B, and a combination thereof, X is one element selected from the group consisting of P, As, Bi, Sb, and a combination thereof, B is one element selected from the group consisting of F, S, and a combination thereof, and 0?z?0.5) particles, and the precursor has a particle diameter of 1 to 20 ?m, a tap density of 0.8 to 2.1 g/cm3, and a specific surface area of 1 to 10 m2/g. The olivine-type positive active material prepared using the olivine-type positive active material precursor has excellent crystallinity of particles, a large particle diameter, and a high tap density, and therefore shows excellent electrochemical characteristics and capacity per unit volume.

Abstract: A sense amplifier driving control circuit has a stable discharge characteristic by differently controlling the discharge of a node having a driving voltage according to the change of an organization of a semiconductor memory device. The sense amplifier driving control circuit includes a pull-down driving block configured to provide a pull-down voltage for a pull-down operation of the sense amplifier, a pull-up driving block configured to sequentially provide a first voltage for the overdrive and a second voltage for the normal drive as a pull-up voltage for a pull-up operation of the sense amplifier, wherein a voltage level of the second voltage is lower than that of the first voltage, and a discharging block configured to discharge the node having the second voltage by controlling a amount of the discharging according to an organization of the semiconductor memory device.

Abstract: A nonvolatile memory device having a memory cell array configured to include a number of memory cells coupled to a bit line, a control circuit configured to output a code signal in response to a verification operation command signal during a verification operation being performed, a page buffer operation voltage generator configured to generate a precharge signal and a sense signal in response to the code signal, and a page buffer configured to precharge the bit line in response to the precharge signal and to sense data programmed into the memory cell in response to the sense signal. A sense signal having a sequentially lowered voltage level is outputted in response to the verification operation being repeatedly performed.

Abstract: A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, including page buffers each configured to store program data for memory cells or store data read from the memory cells, and a control unit configured to, when a program operation is first performed after power is supplied, count a number of program pulses until a verification operation using a first verification voltage is a pass, compare the counted number and a first number of program pulses, select either the first or second program start voltages according to a result of the comparison, and control the program operation to be performed using the selected program start voltage until the power is off.

Abstract: There is provided a frequency synthesizer including a multi-band voltage controlled oscillator having a plurality of voltage controlled oscillating cores outputting oscillation frequencies having different bands according to an input control voltage. Each of the voltage controlled oscillating cores outputs a frequency band divided into a plurality of bands, and the voltage controlled oscillating core operates by each of the divided bands, and one of the voltage controlled oscillating cores operates in one of the bands according to the control voltage. The frequency synthesizer further includes a comparator unit and an oscillation band-determining unit. The comparator unit compares the control voltage with a pre-set reference voltage range. The oscillation band-determining unit changes the band where the voltage controlled oscillating core operates into another one of the bands when the control voltage is out of the pre-set reference voltage range.

Abstract: A frequency conversion circuit comprises an input stage composed of one or more transistors, the input stage outputting a current corresponding to a voltage-type RF signal which is input to the gate of the transistor; a frequency conversion stage receiving an LO signal, causing the output RF signal to transit by the frequency of the LO signal so as to output an IF signal, and detecting an output voltage of the IF signal; a bleeding transistor connected to the input stage, supplying a current corresponding to a DC voltage, applied to a gate-source stage thereof, as a bleeding current to the transistor of the input stage, and in an AC manner, operating complementarily with the input stage to control a current flowing in the frequency conversion stage; a common mode feedback circuit comparing an output voltage provided from the frequency conversion stage with a preset reference voltage, adjusting the output voltage such that the output voltage is equalized to the reference voltage, and directly feeding the adjus

Abstract: An internal voltage discharge circuit includes a differential comparator for differentially comparing a reference voltage with a feedback voltage to generate a discharge control voltage, a level detector for detecting a level of external power supply voltage and a discharge unit for adjusting an amount of discharge of an internal voltage based on the level signal detected by the level detector and the discharge control voltage from the differential comparator.

Abstract: The present invention relates to a fluorine-containing magnesium oxide powder using a vapor phase reaction and a method of preparing the same and more particularly to a fluorine-containing magnesium oxide powder brings about a cathode-luminescence emission having a peak within a wavelength range of 220 to 320 nm upon being excited by electron beams. The present invention provides a fluorine-containing magnesium oxide powder using a vapor phase reaction that sprays fluorine-containing gas and oxygen-containing gas to magnesium vapor, and the purity of magnesium oxide containing fluorine (i.e. the purity of fluorine-containing magnesium oxide) of 0.001 to 2 wt % is at least 98 wt % and a BET specific surface area thereof is 0.1 to 50 m2/g.

Abstract: On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.

Abstract: An output circuit includes a pre-driving unit configured to drive an input signal by using a different driving power according to an output operation mode and generate pull-up and pull-down signals corresponding to the resultant input signal and an output driving unit configured to output data in response to the pull-up and pull-down signals.

Abstract: A sense amplifier driving control circuit has a stable discharge characteristic by differently controlling the discharge of a node having a driving voltage according to the change of an organization of a semiconductor memory device. The sense amplifier driving control circuit includes a pull-down driving block configured to provide a pull-down voltage for a pull-down operation of the sense amplifier, a pull-up driving block configured to sequentially provide a first voltage for the overdrive and a second voltage for the normal drive as a pull-up voltage for a pull-up operation of the sense amplifier, wherein a voltage level of the second voltage is lower than that of the first voltage, and a discharging block configured to discharge the node having the second voltage by controlling a amount of the discharging according to an organization of the semiconductor memory device.

Abstract: There is provided a bias current generating apparatus capable of providing a bias current where a characteristic change is compensated, to one of an analog circuit and RF circuit where various characteristic changes occur according to a temperature, by generating bias currents having a plurality of temperature coefficients.

Abstract: On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.

Abstract: An internal voltage discharge circuit includes a differential comparator for differentially comparing a reference voltage with a feedback voltage to generate a discharge control voltage, a level detector for detecting a level of external power supply voltage and a discharge unit for adjusting an amount of discharge of an internal voltage based on the level signal detected by the level detector and the discharge control voltage from the differential comparator.

Abstract: On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.

Abstract: On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.

Abstract: The present invention relates to an exponential function generator which is realized with only CMOS element without BJT element, not limited by the physical properties of the element or a square circuit, and not complicated in its configuration, and a variable gain amplifier using the same. The exponential function generator includes a voltage-current converter, 1st to nth curve generators for mirroring the current from the voltage-current converter, outputting a current adjusted according to a predetermined ratio, and an output end for outputting the sum of the current from the 1st to nth curve generators. The exponential current generator is configured to generate the current exponentially adjusted according to the control voltage.

Abstract: There is provided a frequency synthesizer including a multi-band voltage controlled oscillator having a plurality of voltage controlled oscillating cores outputting oscillation frequencies having different bands according to an input control voltage. Each of the voltage controlled oscillating cores outputs a frequency band divided into a plurality of bands, and the voltage controlled oscillating core operates by each of the divided bands, and one of the voltage controlled oscillating cores operates in one of the bands according to the control voltage. The frequency synthesizer further includes a comparator unit and an oscillation band-determining unit. The comparator unit compares the control voltage with a pre-set reference voltage range. The oscillation band-determining unit changes the band where the voltage controlled oscillating core operates into another one of the bands when the control voltage is out of the pre-set reference voltage range.

Abstract: An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back bias/pumping voltage detector for detecting a level difference between a back bias/pumping voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias/pumping voltage detector, and a pumping unit for pumping the back bias/pumping voltage according to an activation period of the oscillating signal.

Abstract: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.