Abstract: Provided are an apparatus for manufacturing a textile grid with increased adhesion and a method thereof capable of integrating the textile grid with a concrete structure by increasing the adhesion of the textile grid when the concrete structure is built, repaired, or reinforced, increasing structural safety and durability of the concrete structure, increasing a working speed by coating a surface of the textile grid with an abrasive material powder that is a surface coating material in an automatic series of processes immediately after the textile grid is manufactured, and increasing coating performance by automatically inspecting and adjusting the amount of the coating material applied to the surface of the textile grid using a camera.

Abstract: The present disclosure relates to a biomarker for predicting the sensitivity to a protein kinase inhibitor and a use thereof. The present disclosure provides a marker, a composition, and a kit for predicting the sensitivity to a protein kinase inhibitor, and a prediction method thereof. According to the present disclosure, the marker has an excellent effect of predicting the sensitivity to a protein kinase inhibitor, and thus the present disclosure can be useful for cancer treatment.

Abstract: A method for processing data for discovering a new drug candidate substance by a data processing apparatus includes receiving at least some of omics levels that make up omics through a user interface, receiving at least some types of mutual association degrees among a plurality of types of mutual association degrees, selecting a DB for the at least some of the omics levels and a DB for the at least some types of mutual association from an omics DB including data for each omics level and data for each type of mutual association, generating a first matrix composed of the DB for the at least some of the omics levels and the DB for the at least some types of mutual association degrees, receiving a predetermined search word through the user interface, extracting a plurality of biological entities, and generating a multi-omics network in which a plurality of nodes.

Abstract: Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring conductive lines and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device comprises: a conductive line formed over a substrate; and a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer, and an antioxidant material.

Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.

Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.

Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.

Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.

Abstract: The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.

Abstract: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.

Abstract: A method for fabricating a semiconductor device includes: forming an impurity junction area within an area of the semiconductor substrate; forming a contact hole which partially exposes a surface the impurity junction area; and performing an additional ion implant process to implant impurity ions into the impurity junction area exposed through the contact hole, thereby increasing an impurity concentration of a surface portion of the impurity junction area.

Abstract: A thermal treatment apparatus and method for processing a wafer are provided. The thermal treatment apparatus includes a process chamber for thermally treating the wafer, a heating unit for heating the wafer in the process chamber, and a gas supply unit for supplying a gas and controlling a gas pressure differently by sections of the wafer. The heating unit is provided in at least one of the upper side and the lower side of the process chamber. The heating unit includes a plurality of heater blocks capable of controlling a temperature for sections of the wafer.

Abstract: The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.

Abstract: A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug.

Abstract: The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate and another method for fabricating a semiconductor device capable of improving distribution of transistor parameters inside a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile.

Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

Abstract: A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug.

Abstract: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.

Abstract: A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, forming a gate spacer layer at both sides of the gate stack, and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other.

Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.