Abstract: The present invention relates to a protection of copyrights of digital data, and more particularly, to a real-time blind watermarking method using quantization, in which a watermark information for representing ownership is embedded in a digital image, video or the like so as not to be visually or aurally discriminated and is extracted after various attacks such as edit or the like, and which can be used in all compression ways. The real-time video watermarking system is a blind method and is simple. In order to perform DCT with respect to an original frame and enhance the robustness, the watermark is embedded in a low frequency component. Further, since the DCT is not performed with respect to all blocks, the invention has a rapid operation speed regardless of the size of the video frame.

Abstract: A polypropylene resin composition for automobile interior materials, more particularly to a polypropylene resin composition including a crystalline polypropylene and rubber mixture wherein inorganic filler, atactic polypropylene and process oil are added to offer good flexibility, heat-resistance, cold-resistance, extrusion coating property and calender processing property and to remove offensive odor, which is specially useful for back coat of automobile mats.

Abstract: A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.

Abstract: A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.

Abstract: A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.

Abstract: A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.

Abstract: Load driving circuits are adjusted to drive loads with fewer or more pull-down devices by sensing the load electrically coupled to the load driving circuit. In particular, capacitance of the load is compared to a threshold capacitance. If the capacitance of the load is less than the threshold capacitance, selected ones of the pull-down devices are disabled, thereby reducing the capacity of the load driving circuit. If the capacitance of the load is greater than the threshold capacitance, selected ones of the pull-down devices are enabled, thereby increasing the capacity of the load driving circuit. The pull-down devices include delay circuits that enable selected transistors after a delay.