Patents by Inventor Seung Yong Choi

Seung Yong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9929116
    Abstract: The electronic device module includes a sealing part sealing an electronic component therein, and an external connection terminal disposed on one surface of the sealing part. The electronic device module also includes a dummy bonding part configured on a surface of the sealing part and spaced apart from the external connection terminal.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 27, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seung Yong Choi
  • Publication number: 20170243833
    Abstract: A package module includes first and second components, a conductive wall, and a molding portion. The first component and the second component are disposed on a substrate. The conductive wall is disposed between the first component and the second component. The molding portion is disposed on the first component, the second component, and the conductive wall, and has a slot defining a cavity above an upper portion of the conductive wall.
    Type: Application
    Filed: December 8, 2016
    Publication date: August 24, 2017
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Woo CHOI, Hyun Kook CHO, Il Hyeong LEE, Seung Yong CHOI
  • Publication number: 20170229411
    Abstract: The electronic device module includes a sealing part sealing an electronic component therein, and an external connection terminal disposed on one surface of the sealing part. The electronic device module also includes a dummy bonding part configured on a surface of the sealing part and spaced apart from the external connection terminal.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 10, 2017
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seung Yong CHOI
  • Patent number: 9706661
    Abstract: An electronic device module includes a first substrate having at least one or more electronic devices mounted on one surface thereof, a second substrate bonded to one surface of the first substrate and including at least one device accommodating part having a space in which the electronic device is accommodated, and a shielding member disposed in the device accommodating part and accommodating at least one or more electronic devices therein.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: July 11, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seung Yong Choi
  • Patent number: 9673123
    Abstract: The electronic device module includes a sealing part sealing an electronic component therein, and an external connection terminal disposed on one surface of the sealing part. The electronic device module also includes a dummy bonding part configured on a surface of the sealing part and spaced apart from the external connection terminal.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seung Yong Choi
  • Patent number: 9510461
    Abstract: There is provided an electronic component module capable of increasing a degree of integration by mounting electronic component on both surfaces of a substrate, the module including: a first substrate having mounted electrodes formed on both surfaces thereof; a plurality of electronic components mounted on both surfaces of the first substrate; at least one second substrate bonded to a lower surface of the first substrate; and an insulating part formed in at least one position in a gap between the first substrate and the second substrate and bonding the first substrate to the second bonding substrate.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 29, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Il Hyeong Lee, Jae Cheon Doh, Seung Yong Choi
  • Publication number: 20160086866
    Abstract: The electronic device module includes a sealing part sealing an electronic component therein, and an external connection terminal disposed on one surface of the sealing part. The electronic device module also includes a dummy bonding part configured on a surface of the sealing part and spaced apart from the external connection terminal.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 24, 2016
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seung Yong CHOI
  • Publication number: 20160029486
    Abstract: A solder joint structure may include a first active surface on which a plurality of connection terminals are provided, a second active surface on which a plurality of bonding pads are provided, and a plurality of solder bonding portions bonded to the connection terminals and the bonding pads. A bonding area between the connection terminal and the solder bonding portion may be smaller than a bonding area between the bonding pad and the solder bonding portion.
    Type: Application
    Filed: February 9, 2015
    Publication date: January 28, 2016
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ho JEON, Thomas A. Kim, Kyung In Kang, Seung Yong Choi, Ki Chan Kim
  • Publication number: 20150325529
    Abstract: An electronic device module includes a first substrate having at least one or more electronic devices mounted on one surface thereof, a second substrate bonded to one surface of the first substrate and including at least one device accommodating part having a space in which the electronic device is accommodated, and a shielding member disposed in the device accommodating part and accommodating at least one or more electronic devices therein.
    Type: Application
    Filed: January 29, 2015
    Publication date: November 12, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Seung Yong CHOI
  • Patent number: 9147627
    Abstract: A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: September 29, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
  • Publication number: 20150062854
    Abstract: There are provided an electronic component module in which electronic components are mounted on both surfaces of a substrate to increase integration density, and a method of manufacturing the same, the electronic component module including a first substrate; a plurality of electronic components mounted on both surfaces of the first substrate; a second substrate bonded to a lower surface of the first substrate; and a molded part formed on the lower surface of the first substrate and having the second substrate embedded therein.
    Type: Application
    Filed: May 8, 2014
    Publication date: March 5, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Yong CHOI, II Hyeong LEE, Jae Cheon DOH
  • Publication number: 20140376193
    Abstract: There is provided an electronic component module capable of increasing a degree of integration by mounting electronic component on both surfaces of a substrate, the module including: a first substrate having mounted electrodes formed on both surfaces thereof; a plurality of electronic components mounted on both surfaces of the first substrate; at least one second substrate bonded to a lower surface of the first substrate; and an insulating part formed in at least one position in a gap between the first substrate and the second substrate and bonding the first substrate to the second bonding substrate.
    Type: Application
    Filed: October 7, 2013
    Publication date: December 25, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Il Hyeong LEE, Jae Cheon DOH, Seung Yong CHOI
  • Publication number: 20140217572
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Application
    Filed: November 12, 2013
    Publication date: August 7, 2014
    Applicant: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
    Inventors: Joo-Yang Eom, O-seob Jeon, Seung-Won Lim, Seung-Yong Choi
  • Publication number: 20140145348
    Abstract: Disclosed herein are an RF module and a method of manufacturing the same. According to the exemplary embodiment of the present invention, the RF module includes: an RF IC device provided with a via through which upper and lower surfaces thereof are connected to each other; an electronic component mounted on the upper surface or the lower surface of the RF IC device; a molding material having the electronic component sealed therein to protect the electronic component and formed on the upper or lower surface of the RF IC device; and an auxiliary substrate coupled with the upper or lower surface of the RF IC device and providing a place at which other electronic components other than the electronic component sealed in the molding material are mounted, wherein the auxiliary substrate is provided with a through hole having a predetermined size to mount the other electronic components therein.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Seung Yong CHOI
  • Patent number: 8604606
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 10, 2013
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Patent number: 8168475
    Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: May 1, 2012
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Seung-yong Choi, Min-hyo Park
  • Patent number: 7936054
    Abstract: A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: May 3, 2011
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Joo-yang Eom, Min-hyo Park, Seung-yong Choi
  • Publication number: 20100289137
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Application
    Filed: July 28, 2010
    Publication date: November 18, 2010
    Applicant: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Patent number: 7786570
    Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: August 31, 2010
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Joo-Yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
  • Publication number: 20100203684
    Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.
    Type: Application
    Filed: April 15, 2010
    Publication date: August 12, 2010
    Applicant: Fairchild Korea Semiconductor Ltd.
    Inventors: Seung-yong Choi, Min-hyo Park