Patents by Inventor Seung Yong Choi
Seung Yong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160029486Abstract: A solder joint structure may include a first active surface on which a plurality of connection terminals are provided, a second active surface on which a plurality of bonding pads are provided, and a plurality of solder bonding portions bonded to the connection terminals and the bonding pads. A bonding area between the connection terminal and the solder bonding portion may be smaller than a bonding area between the bonding pad and the solder bonding portion.Type: ApplicationFiled: February 9, 2015Publication date: January 28, 2016Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Young Ho JEON, Thomas A. Kim, Kyung In Kang, Seung Yong Choi, Ki Chan Kim
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Publication number: 20150325529Abstract: An electronic device module includes a first substrate having at least one or more electronic devices mounted on one surface thereof, a second substrate bonded to one surface of the first substrate and including at least one device accommodating part having a space in which the electronic device is accommodated, and a shielding member disposed in the device accommodating part and accommodating at least one or more electronic devices therein.Type: ApplicationFiled: January 29, 2015Publication date: November 12, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Seung Yong CHOI
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Patent number: 9147627Abstract: A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.Type: GrantFiled: November 12, 2009Date of Patent: September 29, 2015Assignee: Fairchild Semiconductor CorporationInventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
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Publication number: 20150062854Abstract: There are provided an electronic component module in which electronic components are mounted on both surfaces of a substrate to increase integration density, and a method of manufacturing the same, the electronic component module including a first substrate; a plurality of electronic components mounted on both surfaces of the first substrate; a second substrate bonded to a lower surface of the first substrate; and a molded part formed on the lower surface of the first substrate and having the second substrate embedded therein.Type: ApplicationFiled: May 8, 2014Publication date: March 5, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Yong CHOI, II Hyeong LEE, Jae Cheon DOH
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Publication number: 20140376193Abstract: There is provided an electronic component module capable of increasing a degree of integration by mounting electronic component on both surfaces of a substrate, the module including: a first substrate having mounted electrodes formed on both surfaces thereof; a plurality of electronic components mounted on both surfaces of the first substrate; at least one second substrate bonded to a lower surface of the first substrate; and an insulating part formed in at least one position in a gap between the first substrate and the second substrate and bonding the first substrate to the second bonding substrate.Type: ApplicationFiled: October 7, 2013Publication date: December 25, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Il Hyeong LEE, Jae Cheon DOH, Seung Yong CHOI
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Publication number: 20140217572Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.Type: ApplicationFiled: November 12, 2013Publication date: August 7, 2014Applicant: FAIRCHILD KOREA SEMICONDUCTOR, LTD.Inventors: Joo-Yang Eom, O-seob Jeon, Seung-Won Lim, Seung-Yong Choi
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Publication number: 20140145348Abstract: Disclosed herein are an RF module and a method of manufacturing the same. According to the exemplary embodiment of the present invention, the RF module includes: an RF IC device provided with a via through which upper and lower surfaces thereof are connected to each other; an electronic component mounted on the upper surface or the lower surface of the RF IC device; a molding material having the electronic component sealed therein to protect the electronic component and formed on the upper or lower surface of the RF IC device; and an auxiliary substrate coupled with the upper or lower surface of the RF IC device and providing a place at which other electronic components other than the electronic component sealed in the molding material are mounted, wherein the auxiliary substrate is provided with a through hole having a predetermined size to mount the other electronic components therein.Type: ApplicationFiled: November 22, 2013Publication date: May 29, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Seung Yong CHOI
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Patent number: 8604606Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.Type: GrantFiled: July 28, 2010Date of Patent: December 10, 2013Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
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Patent number: 8168475Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.Type: GrantFiled: April 15, 2010Date of Patent: May 1, 2012Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Seung-yong Choi, Min-hyo Park
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Patent number: 7936054Abstract: A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon.Type: GrantFiled: December 10, 2008Date of Patent: May 3, 2011Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Joo-yang Eom, Min-hyo Park, Seung-yong Choi
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Publication number: 20100289137Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.Type: ApplicationFiled: July 28, 2010Publication date: November 18, 2010Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
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Patent number: 7786570Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.Type: GrantFiled: January 23, 2009Date of Patent: August 31, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Joo-Yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi
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Publication number: 20100203684Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.Type: ApplicationFiled: April 15, 2010Publication date: August 12, 2010Applicant: Fairchild Korea Semiconductor Ltd.Inventors: Seung-yong Choi, Min-hyo Park
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Publication number: 20100140786Abstract: Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member.Type: ApplicationFiled: December 7, 2009Publication date: June 10, 2010Applicant: FAIRCHILD KOREA SEMICONDUCTOR LTD.Inventors: Keun-hyuk LEE, Young-sun KO, Seung-won LIM, Man-kyo JUNG, Seung-yong CHOI
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Publication number: 20100052127Abstract: A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.Type: ApplicationFiled: November 12, 2009Publication date: March 4, 2010Inventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
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Patent number: 7638861Abstract: The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the leads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.Type: GrantFiled: February 28, 2006Date of Patent: December 29, 2009Assignee: Fairchild Semiconductor CorporationInventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
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Patent number: 7632719Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.Type: GrantFiled: January 7, 2009Date of Patent: December 15, 2009Assignee: Fairchild Korea Semiconductor, LtdInventors: Seung Yong Choi, Min Hyo Park, Ji Hwan Kim, Rajeev Joshi
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Publication number: 20090244848Abstract: Provided are power device substrates that comprise thermally conductive plastic materials, and power device packages including the same. An exemplary power device package includes a power device substrate that comprises a thermally conductive plastic material, and has a first principal plane that provides an electrically insulating surface and a second principal plane of which at least a portion is exposed outside a molding member. The exemplary power device package further includes one or more power devices disposed on the first principal plane of the power device substrate, and a plurality of conductive members that are electrically connected to the power device(s) in order to electrically connect the power device(s) to an external circuit.Type: ApplicationFiled: December 16, 2008Publication date: October 1, 2009Inventors: Seung-won Lim, O-soeb Jeon, Seung-yong Choi, Joon-seo Son, Man-kyo Jong
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Publication number: 20090243079Abstract: Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate body layer being formed of a silicon (Si)-based material; and at least one first semiconductor device which is mounted on the first principal plane.Type: ApplicationFiled: March 17, 2009Publication date: October 1, 2009Inventors: Seung-won Lim, O-seob Jeon, Seung-yong Choi, Joon-seo Son, Man-kyo Jong
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Publication number: 20090194869Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.Type: ApplicationFiled: January 23, 2009Publication date: August 6, 2009Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Joo-yang Eom, O-seob Jeon, Seung-won Lim, Seung-yong Choi