Patents by Inventor Sey-Ping Sun
Sey-Ping Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10867976Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: GrantFiled: December 11, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Patent number: 10797156Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.Type: GrantFiled: December 23, 2019Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
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Publication number: 20200258784Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: May 1, 2020Publication date: August 13, 2020Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 10651091Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: April 22, 2019Date of Patent: May 12, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20200127118Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Inventors: Neng-Kuo CHEN, Clement Hsingjen WANN, Yi-An LIN, Chun-Wei CHANG, Sey-Ping SUN
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Publication number: 20200118984Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Patent number: 10516031Abstract: A method of fabricating a semiconductor device includes depositing a contact etch stop layer (CESL) over a dummy gate electrode, a source/drain (S/D) region and an isolation feature. The method further includes performing a first CMP to expose the dummy gate electrode. The method further includes removing an upper portion of the CESL. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the dummy gate electrode.Type: GrantFiled: October 31, 2017Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
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Patent number: 10510734Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: GrantFiled: November 30, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Publication number: 20190252261Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 10333001Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.Type: GrantFiled: March 26, 2018Date of Patent: June 25, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 10276548Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: GrantFiled: August 4, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Patent number: 10269649Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: March 28, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 10269628Abstract: A contact structure of a semiconductor device is provided. The contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.Type: GrantFiled: February 27, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Ding-Kang Shih, Chin-Hsiang Lin, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20190115326Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: ApplicationFiled: November 30, 2018Publication date: April 18, 2019Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Publication number: 20190006244Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.Type: ApplicationFiled: August 13, 2018Publication date: January 3, 2019Inventors: Sung-Li Wang, Chih-Sheng Chang, Sey-Ping Sun
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Patent number: 10115597Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.Type: GrantFiled: January 30, 2017Date of Patent: October 30, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chi-Yuan Shih, Gin-Chen Huang, Clement Hsingjen Wann, Li-Chi Yu, Chin-Hsiang Lin, Ling-Yen Yeh, Meng-Chun Chang, Neng-Kuo Chen, Sey-Ping Sun, Ta-Chun Ma, Yen-Chun Huang
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Patent number: 10049938Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.Type: GrantFiled: January 16, 2015Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Sung-Li Wang, Chih-Sheng Chang, Sey-Ping Sun
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Publication number: 20180219095Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.Type: ApplicationFiled: March 26, 2018Publication date: August 2, 2018Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20180219077Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: March 28, 2018Publication date: August 2, 2018Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9941367Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: August 2, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann