Patents by Inventor Sey-Ping Sun
Sey-Ping Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170140942Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Inventors: Chun Hsiung Tsai, Chi-Yuan Shih, Gin-Chen Huang, Clement Hsingjen Wann, Li-Chi Yu, Chin-Hsiang Lin, Ling-Yen Yeh, Meng-Chun Chang, Neng-Kuo Chen, Sey-Ping Sun, Ta-Chun Ma, Yen-Chun Huang
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Patent number: 9607826Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.Type: GrantFiled: April 13, 2015Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9601587Abstract: A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape.Type: GrantFiled: January 23, 2015Date of Patent: March 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sey-Ping Sun, Tsung-Lin Lee, Chin-Hsiang Lin, Chih-Hao Chang, Chen-Nan Yeh, Chao-An Jong
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Patent number: 9589803Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.Type: GrantFiled: August 10, 2012Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
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Patent number: 9589838Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.Type: GrantFiled: June 26, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Ding-Kang Shih, Chin-Hsiang Lin, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9559182Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.Type: GrantFiled: December 14, 2015Date of Patent: January 31, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Sey-Ping Sun, Ling-Yen Yeh, Chi-Yuan Shih, Li-Chi Yu, Chun Hsiung Tsai, Chin-Hsiang Lin, Neng-Kuo Chen, Meng-Chun Chang, Ta-Chun Ma, Gin-Chen Huang, Yen-Chun Huang
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Publication number: 20160380103Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.Type: ApplicationFiled: September 12, 2016Publication date: December 29, 2016Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20160343815Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20160329329Abstract: An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.Type: ApplicationFiled: July 19, 2016Publication date: November 10, 2016Inventors: Neng-Kuo Chen, Gin-Chen Huang, Ching-Hong Jiang, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20160329215Abstract: The present disclosure relates to a method of performing a chemical mechanical planarization (CMP) process with a high germanium-to-oxide removal selectivity and a low rate of germanium recess formation. The method is performed by providing a semiconductor substrate having a plurality of germanium compound regions including germanium interspersed between a plurality of oxide regions including an oxide. A slurry is then provided onto the semiconductor substrate. The slurry has an oxidant and an etching inhibitor configured to reduce a removal rate of the germanium relative to the oxide. A CMP process is then performed by bringing a chemical mechanical polishing pad in contact with top surfaces of the plurality of germanium compound regions and the plurality of oxide regions.Type: ApplicationFiled: July 21, 2016Publication date: November 10, 2016Inventors: Chia-Jung Hsu, Yun-Lung Ho, Neng-Kuo Chen, Wen-Feng Chueh, Sey-Ping Sun, Song-Yuan Chang
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Patent number: 9443964Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.Type: GrantFiled: July 7, 2015Date of Patent: September 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9443769Abstract: Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces.Type: GrantFiled: April 21, 2014Date of Patent: September 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9416297Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) slurry composition that provides for a high metal to dielectric material selectivity along with a low rate of metal recess formation. In some embodiments, the disclosed slurry composition has an oxidant and an etching inhibitor. The oxidant has a compound with one or more oxygen molecules. The etching inhibitor has a nitrogen-oxide compound. The etching inhibitor reduces the rate of metal and dielectric material (e.g., oxide) removal, but does so in a manner that reduces the rate of dielectric material removal by a larger amount, so as to provide the slurry composition with a high metal (e.g., germanium) to dielectric material removal selectivity and with a low rate of metal recess formation.Type: GrantFiled: November 13, 2013Date of Patent: August 16, 2016Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., UWiZ Technology Co., Ltd.Inventors: Chia-Jung Hsu, Yun-Lung Ho, Neng-Kuo Chen, Wen-Feng Chueh, Sey-Ping Sun, Song-Yuan Chang
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Publication number: 20160211338Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.Type: ApplicationFiled: January 16, 2015Publication date: July 21, 2016Inventors: Sung-Li Wang, Chih-Sheng Chang, Sey-Ping Sun
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Patent number: 9368446Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.Type: GrantFiled: December 29, 2014Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9337103Abstract: A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.Type: GrantFiled: December 7, 2012Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-An Lin, Chun-Wei Chang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20160099331Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.Type: ApplicationFiled: December 14, 2015Publication date: April 7, 2016Inventors: Clement Hsingjen Wann, Sey-Ping Sun, Ling-Yen Yeh, Chi-Yuan Shih, Li-Chi Yu, Chun Hsiung Tsai, Chin-Hsiang Lin, Neng-Kuo Chen, Meng-Chun Chang, Ta-Chun Ma, Gin-Chen Huang, Yen-Chun Huang
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Patent number: 9263252Abstract: This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.Type: GrantFiled: January 7, 2013Date of Patent: February 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei Chang, Yi-An Lin, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann, Yu-Lien Huang
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Patent number: 9214556Abstract: A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals.Type: GrantFiled: August 9, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Sey-Ping Sun, Ling-Yen Yeh, Chi-Yuan Shih, Li-Chi Yu, Chun Hsiung Tsai, Chin-Hsiang Lin, Neng-Kuo Chen, Meng-Chun Chang, Ta-Chun Ma, Gin-Chen Huang, Yen-Chun Huang
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Publication number: 20150311321Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.Type: ApplicationFiled: July 7, 2015Publication date: October 29, 2015Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann