Abstract: A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process.

Abstract: A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N2O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N2O plasma is created by applying RF power to a showerhead from which the N2O is dispensed. By reacting an N2O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 Å and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N2O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N2O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N2O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation.

Abstract: A method for fabricating an integrated circuit is presented. In the method, a dielectric layer is formed, and then a conductive layer is formed upon the dielectric layer. A base gate may then be patterned from the conductive layer. An intergate dielectric is preferably formed over and around the base gate. A spacer gate may then be formed such that at least a portion of the spacer gate is elevationally below an upper portion of the base gate. At least a portion of the intergate dielectric layer is preferably interposed between a sidewall surface of the spacer gate and a sidewall surface of the base gate. The final memory cell fabricated in this manner does not need to transfer electrons from a semiconducting substrate during operation.

Abstract: An ultrathin gate dielectric and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A low-power, low-pressure plasma-enhanced chemical vapor deposition (PECVD) method employing silane and nitrous oxide sources is used to deposit the dielectric. As compared to conventional PECVD deposition, the method uses lower silane and nitrous oxide flow rates, a more dilute silane in nitrogen mixture, a lower chamber pressure, and a lower radio frequency power density. These settings allow plasma conditions to stabilize so that deposition may be performed in time increments at least as short as 0.1 second, so that oxide thicknesses at least as small as one angstrom may be controllably deposited. The oxide is preferably deposited in portions at multiple substrate mounting positions in a deposition chamber.

Abstract: The present invention is directed to a method of forming process layers comprised of silicon nitride. In one embodiment, the method comprises forming a silicon nitride layer using silane volumes ranging from approximately 350-390 standard cubic centimeters.

Abstract: A method is provided for forming high quality nitride sidewall spacers laterally adjacent to the opposed sidewall surfaces of a gate conductor dielectrically spaced above a semiconductor substrate. In an embodiment, a polysilicon gate conductor is provided which is arranged between a pair of opposed sidewall surfaces upon a gate dielectric. The gate dielectric is arranged upon a semiconductor substrate. Nitride is deposited from a high density plasma source across exposed surfaces of the substrate and the gate conductor. The high density plasma source may be generated within an ECR or ICP reactor containing a gas bearing N2 and SiH4. The energy and flux of electrons, ions, and radicals within the plasma are strictly controlled by the magnetic field such that a substantially stoichiometric and contaminant-free nitride is deposited upon the semiconductor topography. Thereafter, the nitride is anisotropically etched so as to form nitride spacers laterally adjacent the sidewall surfaces of the gate conductor.

Abstract: Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.

Abstract: A semiconductor device is provided and formed using self-aligned metal-containing gates within a metal-oxide semiconductor (MOS) process. After forming junction regions within a semiconductor substrate, the gate conductor, or junction implant alignment structure, is at least partially removed to form a trench within a dielectric formed above the substrate. Upper surfaces of the transistor, except the upper surface of the gate conductor, are thereby protected by the dielectric. A metal-containing material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The metal material can be formed either as a single layer or as multiple metal and/or dielectric layers interposed throughout the as-filled trench. The metal-filled trench formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.

Abstract: An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use in integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.

Abstract: A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.

Abstract: An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiO.sub.x N.sub.y stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiO.sub.x N.sub.y stop layer within the CVD reactor chamber. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.

Abstract: The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.

Abstract: A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.

Abstract: A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process.