Patents by Inventor Se-Young Yang
Se-Young Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969397Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.Type: GrantFiled: November 7, 2019Date of Patent: April 30, 2024Assignee: THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Mi-La Cho, Dong-Yun Shin, Jong-Young Choi, Chul-Woo Yang, Sung-Hwan Park, Seon-Yeong Lee, Min-Jung Park, Joo-Yeon Jhun, Se-Young Kim, Hyeon-Beom Seo, Jae-Yoon Ryu, Keun-Hyung Cho
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Publication number: 20240111848Abstract: An example electronic device includes a display, a communication circuit, a memory, and at least one processor configured to, based on a signal for requesting transmission of identification information including a call word for using first mode of an artificial intelligence assistant function of the electronic device being received, from another electronic device, through the communication circuit using first communication method, control the display to display a user interface for requesting user confirmation for transmission of the identification information; control the communication circuit to transmit the identification information to the another electronic device as a result of user confirmation through the user interface; and receive information for using a second communication method from the another electronic device.Type: ApplicationFiled: December 8, 2023Publication date: April 4, 2024Inventors: Chang-bae YOON, Jeong-in KIM, Se-won OH, Hyo-young CHO, Kyung-rae KIM, Hee-jung KIM, Hyun-jin YANG, Ji-won CHA
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Publication number: 20240055393Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: ApplicationFiled: July 12, 2023Publication date: February 15, 2024Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 11735563Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: GrantFiled: October 27, 2021Date of Patent: August 22, 2023Assignee: Invensas LLCInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Publication number: 20220165703Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: ApplicationFiled: October 27, 2021Publication date: May 26, 2022Applicant: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 11189595Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: GrantFiled: August 21, 2020Date of Patent: November 30, 2021Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Publication number: 20210035948Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: ApplicationFiled: August 21, 2020Publication date: February 4, 2021Applicant: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 10756049Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: GrantFiled: September 8, 2017Date of Patent: August 25, 2020Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 10181455Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.Type: GrantFiled: January 17, 2017Date of Patent: January 15, 2019Assignee: Apple Inc.Inventors: Jun Zhai, Chonghua Zhong, Kunzhong Hu, Se Young Yang
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Publication number: 20180204820Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.Type: ApplicationFiled: January 17, 2017Publication date: July 19, 2018Inventors: Jun Zhai, Chonghua Zhong, Kunzhong Hu, Se Young Yang
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Publication number: 20180026007Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: ApplicationFiled: September 8, 2017Publication date: January 25, 2018Applicant: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 9761558Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: GrantFiled: May 21, 2015Date of Patent: September 12, 2017Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 9659907Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.Type: GrantFiled: April 7, 2015Date of Patent: May 23, 2017Assignee: Apple Inc.Inventors: Jun Zhai, Kunzhong Hu, Chonghua Zhong, Mengzhi Pang, Se Young Yang
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Patent number: 9633974Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.Type: GrantFiled: March 4, 2015Date of Patent: April 25, 2017Assignee: Apple Inc.Inventors: Jun Zhai, Kunzhong Hu, Kwan-Yu Lai, Mengzhi Pang, Chonghua Zhong, Se Young Yang
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Patent number: 9601398Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.Type: GrantFiled: September 29, 2014Date of Patent: March 21, 2017Assignee: Invensas CorporationInventors: Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey, Cyprian Emeka Uzoh
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Publication number: 20160300813Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.Type: ApplicationFiled: April 7, 2015Publication date: October 13, 2016Inventors: Jun Zhai, Kunzhong Hu, Chonghua Zhong, Mengzhi Pang, Se Young Yang
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Publication number: 20160260684Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.Type: ApplicationFiled: March 4, 2015Publication date: September 8, 2016Inventors: Jun Zhai, Kunzhong Hu, Kwan-Yu Lai, Mengzhi Pang, Chonghua Zhong, Se Young Yang
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Patent number: 9252122Abstract: A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.Type: GrantFiled: August 14, 2013Date of Patent: February 2, 2016Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 9236355Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.Type: GrantFiled: July 15, 2014Date of Patent: January 12, 2016Assignee: Apple Inc.Inventors: Jun Zhai, Mengzhi Pang, Se Young Yang, Leland W. Lew
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Publication number: 20150364454Abstract: In some embodiments, it is desirable to increase memory bandwidth using an integrated solution. In one embodiment, wide I/O memory may be used. Described herein are embodiments of systems and methods of reconfiguring wide I/O memory modules. The reconfigured memory modules may be configured such that the memory modules function in combination with current packaging architectures.Type: ApplicationFiled: December 3, 2014Publication date: December 17, 2015Inventors: Jun Zhai, Chonghua Zhong, Kunzhong Hu, Se Young Yang