Abstract: The present disclosure is directed to systems and methods for determining sheet resistance values in a liquid crystal display (LCD) panel. In certain embodiments, a system for determining sheet resistance values in an LCD panel may include a display driver integrated circuit (IC). The display driver IC may include a first switch coupled to a first input/output (I/O) pad and a second I/O pad such that the first I/O pad is configured to couple to a voltage source and the second I/O pad is configured to couple to a current source. The display driver IC may also include a second switch coupled to a third I/O pad and the second I/O pa such that the second switch has substantially the same geometry as the first switch and the third I/O pad is configured to couple to a thin-film transistor (TFT) layer of the display panel.

Abstract: A resistor having a known resistance is coupled in series with a device under test (DUT) having an unknown capacitance. An ac signal source having a known fundamental frequency is coupled to drive the resistor to thereby produce a first ac signal. A phase controllable signal generator produces a second ac signal. The first and second ac signals are fed to a mixer. An output of the mixer is low pass filtered. A peak detector monitors the low pass filtered output while sweeping the phase controllable signal generator, until a peak is detected. The set phase corresponding to the detected peak is then used to obtain an estimate of the unknown DUT capacitance. Other embodiments are also described and claimed.

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract: Systems, methods, and devices are provided to reduce or eliminate mura artifacts on electronic displays. For example, pixels may be programmed to a uniform gray level before all or a substantial number of gates of the pixels are activated. The voltages on some or all source lines that supply the pixels may be measured. A mura artifact may be seen when voltage differences on the source lines are present. As such, operational parameters of the electronic display may be adjusted to reduce or eliminate the mura artifact by reducing the voltage differences.

Abstract: Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A threshold voltage of a constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be measured using a replica component that emulates the behavior of the component.

Abstract: Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be characterized using a replica component that emulates the behavior of the component.

Abstract: Better performance can be provided for a display system that has semiconductor microelectronic components such as demultiplexors, gate line and data line drivers, and pixel switches formed on the display substrate, e.g., a glass substrate that constitutes part of an active matrix display panel. A gate source capacitance of a constituent transistor of one of these microelectronic components, e.g., a pixel thin film transistor (TFT) that is part of a particular display element, may be measured using a replica component that emulates the behavior of the component.

Abstract: A display is disclosed that includes a transparent substrate and a plurality of pixel transistors that are formed on the transparent substrate to generate an image for display. A transistor drive circuit is used to drive the pixel transistors to generate the image. The transistor drive circuit may include a gate driver. Further, a test circuit may be used to: adjust voltages that are applied by the gate driver to a pixel transistor; and determine the voltage of the gate driver when a current spike has occurred to the pixel transistor which causes the pixel transistor to turn on. Once this threshold voltage for the gate driver to turn on the pixel transistor has been determined, it may be stored in a storage device for future use by the gate driver. Other embodiments are also described and claimed.

Abstract: Systems, devices, and methods for using clock detector circuitry to reduce turn-on time of an electronic display, improve image quality, and reduce operations of a host are provided. In one example, a system may include a host configured to transmit a number of signals and a display driver coupled to the host. The number of signals may include a clock signal and data signals. The display driver is configured to drive a display based at least in part on the data signals. The display driver is also configured to be reset upon detection of the clock signal without waiting for a host-issued reset signal. A clock detect circuit configured to detect the clock signal may be configured to transmit an internal reset signal to reset the display driver without a dedicated host-issued reset signal.

Abstract: A display system includes a display panel of pixels, a gate driver and a compensation unit. The gate driver receives a control signal and based on the control signal, generates a gate signal to drive a transistor included in a pixel. The compensation unit measures and compensates for a fall time of the gate driver. The compensation unit includes a replica gate driver, a peak RMS detector, a comparator and a counter. The replica gate driver generates a replica gate signal based on the control signal. The peak RMS detector calculates a peak RMS of the replica gate signal. The comparator compares the peak RMS of the replica gate signal and a reference voltage and generates a comparator value. The counter is controlled by the comparator value to generate a compensation value used to adjust the gate driver and the replica gate driver. Other embodiments are also described and claimed.

Abstract: A system and device for reducing ground bounce in circuitry. Utilization of a common ground supplied to multiple integrated circuits reduces the complexity and costs of producing circuitry but tends to interfere with signal quality within the circuitry by subjecting each integrated circuit to the ground bounce of every other integrated circuit. By introducing a source follower to selectively decouple and/or couple slave circuits within the circuitry, the ground bounce for the overall system can be reduced, thereby increasing the efficiency of interpreting signals within the circuitry.

Abstract: A display system has a display panel in which there are a first subset of pixels and a second subset of pixels. A first common voltage generation circuit drives a first common voltage line that is coupled to the first subset, and a second common voltage generation circuit drives a second common voltage line that is coupled to the second subset. A difference circuit has an input coupled to a first node of a pixel in the first subset, and a further input coupled to a first node of a pixel in the second subset. The difference circuit generates a sensed pixel signal difference. The second common voltage generation uses the sensed difference to compensate for pixel leakage differences between the pixels of the first and second subsets. Other embodiments are also described and claimed.

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract: An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output.

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract: An IC includes first and second pads. The first pad is configured to receive an external clock. Alternatively, the first and second pads are configured to be coupled to a crystal oscillator and receive a reference clock. Alternatively, the second pad is configured to be grounded. The IC includes an internal oscillator for generating an internal clock, and an oscillator detector coupled to the second pad. The oscillator detector includes a transistor having a gate coupled to the second pad configured to pull a source-drain region to a first state if the second pad receives the reference clock or allow the source-drain region to be pulled to a second state if the second pad is grounded. The IC includes a buffer for transferring the first state to the internal oscillator for keeping the internal oscillator enabled and transferring the second state to the internal oscillator for disabling the internal oscillator.

Abstract: The present disclosure includes systems and techniques relating to low power current-voltage mixed ADC architecture. In some implementations, an apparatus includes sample and hold circuitry, at least one ADC module configured to generate a first digital output based on a first analog input provided to the sample and hold circuitry, and current generation circuitry configured to modulate an analog output of the sample and hold circuitry to generate a residue output corresponding to the first analog input absent at least a portion corresponding to the first digital output, and to provide the residue output as a second analog input to further circuitry to generate a second digital output.

Abstract: A finger metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit. First and second side portions include a plurality of first and second finger sections extending in the plurality of metal layers and first and second hole vias connecting the first and second finger sections, respectively. A middle portion connects the first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. A plurality of “T”-shaped sections are defined in the plurality of metal layers and third hole vias connecting the plurality of “T”-shaped sections. Middle portions of the plurality of “T”-shaped sections extend towards the middle portion and between the first side portion and the second side portion of the outer conducting structure.

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract: Circuits having corresponding methods and computer-readable media comprise: an amplifier; a crystal port configured to be electrically coupled to a crystal, wherein a first terminal of the crystal port is electrically coupled to an input of the amplifier, and wherein a second terminal of the crystal port is electrically coupled to an output of the amplifier; a first capacitor, wherein a first terminal of the first capacitor is electrically coupled to ground; a second capacitor, wherein a first terminal of the second capacitor is electrically coupled to ground; a first switch configured to selectively electrically couple the input of the amplifier to a second terminal of the first capacitor; and a second switch configured to selectively electrically couple the output of the amplifier to a second terminal of the second capacitor.