Patents by Inventor Shakti Singh

Shakti Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107486
    Abstract: A method of operating a grain harvesting machine includes: capturing images of a crop material flow in an image capture area of the grain harvesting machine; identifying a plurality of grain elements in the images; determining a velocity of each of the grain elements; determining whether each of the grain elements is likely to be overblown out of the grain harvesting machine based at least in part on the velocity of each of the grain elements; and controlling a subsystem of the grain harvesting machine at least in part based upon the determination of whether the grain elements are likely to be overblown. A grain harvesting machine for performing such a method is also disclosed.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Inventors: Nathan R. Vandike, RANA SHAKTI SINGH
  • Publication number: 20250089220
    Abstract: The present invention provides an efficient hardware architecture for an ORAN compliant thermal management module for a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.
    Type: Application
    Filed: March 24, 2023
    Publication date: March 13, 2025
    Inventors: Narender KUMAR, Shakti SINGH, Amrish BANSAL, Brijesh SHAH, Bajinder Pal SINGH, Selvakumar GANESAN
  • Publication number: 20250072325
    Abstract: A method of operating a grain harvesting machine includes: capturing images of a crop material flow in an image capture area of the grain harvesting machine, the crop material flow including known grain elements, known material other than grain (MOG) elements, and unknown elements not yet identified as grain or MOG; identifying one or more of the unknown elements in the images; determining a velocity of each of the identified unknown elements; based on the velocity of each of the identified unknown elements, determining whether each of the identified unknown elements is grain or MOG; and controlling a subsystem of the grain harvesting machine at least in part based upon the determination of whether each of the identified unknown elements is grain or MOG.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventors: Rana Shakti SINGH, Nathan R. VANDIKE
  • Patent number: 12232444
    Abstract: A cleaning fan on an agricultural harvester generates airflow along an airflow path through a fan duct. A movable flap is mounted relative to the fan duct and controlled to divert the airflow path in a side-to-side transverse direction relative to a front-to-back longitudinal axis of the agricultural harvester.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: February 25, 2025
    Assignee: Deere & Company
    Inventors: Rana Shakti Singh, Mehul Bhavsar, Santosh Khadasare, Abhishek Kumar Roy
  • Publication number: 20250055491
    Abstract: The present invention provides an efficient hardware architecture for an ORAN compliant internal structure of a gnodeB (gNodeB) comprising of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing Level 1, 2 and 3 scheduling in a network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.
    Type: Application
    Filed: March 24, 2023
    Publication date: February 13, 2025
    Inventors: Narender KUMAR, Shakti SINGH, Amrish BANSAL, Brijesh SHAH, Bajinder Pal SINGH, Selvakumar GANESAN
  • Publication number: 20250015915
    Abstract: The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.
    Type: Application
    Filed: March 24, 2023
    Publication date: January 9, 2025
    Inventors: Narender KUMAR, Shakti SINGH, Amrish BANSAL, Brijesh SHAH, Bajinder Pal SINGH, Selvakumar GANESAN
  • Publication number: 20250016040
    Abstract: The present invention provides an efficient hardware architecture of an Ethernet controller to provide for connectivity interfaces to a combined centralized unit and a distributed unit (CCDU) for processing Level 1, 2 and 3 scheduling in a network. The CCDU design may provide the functionality of a CU and a DU as a single unit and the design of the Ethernet controller along with an eASIC comprising an accelerator unit is very important. A single board approach of the CCDU make the CCDU more reliable and less costly.
    Type: Application
    Filed: March 24, 2023
    Publication date: January 9, 2025
    Inventors: Narender KUMAR, Shakti SINGH, Amrish BANSAL, Brijesh SHAH, Bajinder Pal SINGH, Selvakumar Ganesan
  • Patent number: 11971448
    Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: April 30, 2024
    Assignee: Ceremorphic, Inc.
    Inventors: Robert F. Wiser, Shakti Singh, Neelam Surana
  • Publication number: 20240001785
    Abstract: A charger includes a buck converter; and a converter connected to the buck converter. The converter is either a totem pole BL boost structure at the input side, a switched inductor Cuk converter at the output side, or a BL Zeta converter. The charger may be a type-I on-board EV charger or a type-II on-board EV charger.
    Type: Application
    Filed: November 23, 2021
    Publication date: January 4, 2024
    Inventors: Vinod Madhavrao KHADKIKAR, Radha KUSHWAHA, Hatem ZEINELDIN, Hadi OTROK, Rabeb MIZOUNI, Shakti SINGH, Umesh Shantaveerappa BAKTHARAHALLI, Amarendra EDPUGANTI, Abass Afolabi YAHAYA
  • Publication number: 20230296672
    Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
    Type: Application
    Filed: May 9, 2023
    Publication date: September 21, 2023
    Applicant: Ceremorphic, Inc.
    Inventors: Robert F. Wiser, Shakti SINGH, Neelam SURANA
  • Patent number: 11693056
    Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: July 4, 2023
    Assignee: Ceremorphic, Inc.
    Inventors: Robert F. Wiser, Shakti Singh, Neelam Surana
  • Publication number: 20230194607
    Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: Ceremorphic, Inc.
    Inventors: Shakti SINGH, Neelam SURANA, Robert F. Wiser
  • Patent number: 11605609
    Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: March 14, 2023
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Publication number: 20230039498
    Abstract: A cleaning fan on an agricultural harvester generates airflow along an airflow path through a fan duct. A movable flap is mounted relative to the fan duct and controlled to divert the airflow path in a side-to-side transverse direction relative to a front-to-back longitudinal axis of the agricultural harvester.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: Rana Shakti SINGH, Mehul BHAVSAR, Santosh KHADASARE, Abhishek Kumar ROY
  • Patent number: 11421162
    Abstract: The present invention relates to a process for converting the waste plastics along with the petroleum feedstock in a Catalytic Cracking Unit, in particular a Fluid Catalytic Cracking Unit employed in petroleum refineries. The invention also provides a method and hardware system to enable waste plastic to fuel conversion along with hydrocarbon catalytic cracking. The invented process aims to convert any type of waste plastic including polystyrene, polypropylene, polyethylene, metal containing Polyethylene-Polypropylene multilayer plastics & other metal containing plastics along with the petroleum derived feedstock such as vacuum gas oil, reduced crude oil, vacuum residue etc. in catalytic cracking unit.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: August 23, 2022
    Assignee: INDIAN OIL CORPORATION LIMITED
    Inventors: Ponoly Ramachandran Pradeep, Prantik Mondal, Shivam Ashok Dixit, Shikha Saluja, Shakti Singh, Terapalli Hari Venkata Devi Prasad, Satyen Kumar Das, Madhusudan Sau, Gurpreet Singh Kapur, Sankara Sri Venkata Ramakumar
  • Patent number: 11274257
    Abstract: The present invention provides a process for a production of light olefins and aromatics from cracked light naphtha by selective cracking. The present invention thus provides a process for up grading cracked olefinic naphtha to high value petrochemical feed stocks. This process is based on catalytic cracking in which the catalyst activity is optimized by depositing coke for production of light olefins and aromatics. The proposed process has high flexibility and can be operated either in maximizing olefins as reflected from the PIE ratio or in maximizing aromatics (BTX) at different modes of operation depending upon the product requirement.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 15, 2022
    Assignee: Indian Oil Corporation Limited
    Inventors: Subramani Saravanan, Bandaru Venkata Hari Prasadgupta, Prosenjit Maji, Shoeb Hussain Khan, Jagdev Kumar Dixit, Shakti Singh, Reshmi Manna, Madhusudan Sau, Debasis Bhattacharyya, Sanjiv Kumar Mazumdar, Sankara Sri Venkata Ramakumar
  • Publication number: 20220041940
    Abstract: The present invention relates to a process for converting the waste plastics along with the petroleum feedstock in a Catalytic Cracking Unit, in particular a Fluid Catalytic Cracking Unit employed in petroleum refineries. The invention also provides a method and hardware system to enable waste plastic to fuel conversion along with hydrocarbon catalytic cracking. The invented process aims to convert any type of waste plastic including polystyrene, polypropylene, polyethylene, metal containing Polyethylene-Polypropylene multilayer plastics & other metal containing plastics along with the petroleum derived feedstock such as vacuum gas oil, reduced crude oil, vacuum residue etc. in catalytic cracking unit.
    Type: Application
    Filed: August 2, 2021
    Publication date: February 10, 2022
    Inventors: Ponoly Ramachandran PRADEEP, Prantik MONDAL, Shivam Ashok DIXIT, Shikha SALUJA, Shakti SINGH, Terapalli Hari Venkata Devi PRASAD, Satyen Kumar DAS, Madhusudan SAU, Gurpreet Singh KAPUR, Sankara Sri Venkata RAMAKUMAR
  • Publication number: 20210030852
    Abstract: Disclosed herein are compositions and methods for treating and immunizing against C. auris infection and colonization. The compositions and methods include polypeptides and fragments derived from the C. albicans Als3 protein, homologs thereof, and antibodies or fragments thereof that specifically bind these polypeptides and fragments. Administration of these compositions confers treatment and resistance against C. auris infection and colonization.
    Type: Application
    Filed: April 10, 2018
    Publication date: February 4, 2021
    Inventors: John E. EDWARDS, Jr., Shakti SINGH, Ashraf S. IBRAHIM, Priya UPPULURI
  • Publication number: 20200185349
    Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 10667429
    Abstract: A system, such as a heat exchange assembly includes a support structure having a recess, a first support end, a second support end, and a support portion extending between the first and second support ends. The support structure further includes a plurality of projections protruding from a portion of a surface of the support structure, corresponding to the support portion. The support structure is a primary heat sink. The heat exchange assembly includes a vapor chamber having a casing and a wick disposed within the casing. The vapor chamber is disposed within the recess and coupled to a surface of the support structure such that the plurality of projections surrounds the vapor chamber. The casing includes a mid projected portion disposed at an evaporator portion of the vapor chamber. The first and second support ends, and the mid projected portion include a non-uniform surface configured to contact the circuit card.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 26, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Shakti Singh Chauhan, Hendrik Pieter Jacobus De Bock, Graham Charles Kirk, Stanton Earl Weaver, Jr., David Shannon Slaton, Tao Deng, Pramod Chamarthy