Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract: A heat transfer device includes a casing and a wick disposed within the casing. The wick includes a first sintered layer and a second sintered layer. The first sintered layer includes a plurality of first sintered particles, having a first porosity and a plurality of first pores. The first sintered layer is disposed proximate to an inner surface of the casing. The second sintered layer includes a plurality of second sintered particles, having a second porosity and a plurality of second pores. The second sintered layer is disposed on the first sintered layer. The heat transfer device includes at least one first sintered particle smaller than at least one second pore and the first porosity is smaller than the second porosity.

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract: A heat exchange assembly for use in cooling an electrical component is described herein. The heat assembly includes a casing that includes an evaporator section, a condenser section, and a transport section extending between the evaporator section and the condenser section along a longitudinal axis. The casing is configured to bend along a bending axis oriented with respect to the transport section. The casing also includes at least one sidewall that includes at least one fluid chamber extending between the evaporator section and the condenser section to channel a working fluid between the evaporator section and the condenser section. A plurality of fluid channels are defined within the inner surface to channel liquid fluid from the condenser section to the evaporator section. At least one vapor channel is defined within the inner surface to channel gaseous fluid from the evaporator section to the condenser section.

Abstract: An electrical device is described herein. The electrical device includes a housing that includes an inner surface that defines a cavity, a heat sink that is coupled to the housing and oriented along a first plane, and at least one electrical component positioned within the housing cavity and oriented along a second plane that is different than the first plane. A heat exchange assembly is coupled to the electrical component and the heat sink for adjusting a temperature of the electrical component. The heat exchange assembly includes an evaporator section, a condenser section, and a transport section extending between the evaporator section and the condenser section for channeling a working fluid between the evaporator section and the condenser section. The heat exchange assembly is configured to bend along at least one bending axis oriented with respect to the transport section.

Abstract: A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure.

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract: A heat exchange assembly for use in cooling an electrical component is described herein. The heat assembly includes a casing that includes an evaporator section, a condenser section, and a transport section extending between the evaporator section and the condenser section along a longitudinal axis. The casing is configured to bend along a bending axis oriented with respect to the transport section. The casing also includes at least one sidewall that includes at least one fluid chamber extending between the evaporator section and the condenser section to channel a working fluid between the evaporator section and the condenser section. A plurality of fluid channels are defined within the inner surface to channel liquid fluid from the condenser section to the evaporator section. At least one vapor channel is defined within the inner surface to channel gaseous fluid from the evaporator section to the condenser section.

Abstract: An electrical device is described herein. The electrical device includes a housing that includes an inner surface that defines a cavity, a heat sink that is coupled to the housing and oriented along a first plane, and at least one electrical component positioned within the housing cavity and oriented along a second plane that is different than the first plane. A heat exchange assembly is coupled to the electrical component and the heat sink for adjusting a temperature of the electrical component. The heat exchange assembly includes an evaporator section, a condenser section, and a transport section extending between the evaporator section and the condenser section for channeling a working fluid between the evaporator section and the condenser section. The heat exchange assembly is configured to bend along at least one bending axis oriented with respect to the transport section.

Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.

Abstract: Disclosed herein is a heat transfer device that includes a shell; the shell being an enclosure that prevents matter from within the shell from being exchanged with matter outside the shell during the operation of the heat transfer device; the shell having an outer surface and an inner surface; and a porous layer disposed on the inner surface of the shell; the porous particle layer having a thickness effective to enclose a vapor space between opposing faces; the vapor space being effective to provide a passage for the transport of a fluid; the heat transfer device having a thermal conductivity of greater than or equal to about 10 watts per meter-Kelvin and a coefficient of thermal expansion that is substantially similar to that of a semiconductor.

Abstract: Novel 2-substituted methyl penam derivatives include the formula (I), their analogs, their tautomeric forms, their stereoisomers, their polymorphs, their solvates, their pharmaceutically acceptable salts, and pharmaceutical compositions containing them; wherein A=C or N; Het is a three- to seven-membered heterocyclic ring; R1 represents carboxylate anion, or —COOR4 where R4 represents hydrogen, carboxylic acid protecting group or a pharmaceutically acceptable salt; R2 and R3 may be same or different and independently represent hydrogen, halogen, amino, alkyl, protected amino, optionally substituted alkyl, alkenyl, alkynyl and the like; R represents substituted or unsubstituted alkyl, alkenyl, aryl, aralkyl, cycloalkyl, heterocyclyl or heterocyclylalkyl.

Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.

Abstract: Novel 2-substituted methyl penam derivatives include the formula (I), their analogs, their tautomeric forms, their stereoisomers, their polymorphs, their solvates, their pharmaceutically acceptable salts, and pharmaceutical compositions containing them; wherein A=C or N; Het is a three- to seven-membered heterocyclic ring; R1 represents carboxylate anion, or —COOR4 where R4 represents hydrogen, carboxylic acid protecting group or a pharmaceutically acceptable salt; R2 and R3 may be same or different and independently represent hydrogen, halogen, amino, alkyl, protected amino, optionally substituted alkyl, alkenyl, alkynyl and the like; R represents substituted or unsubstituted alkyl, alkenyl, aryl, aralkyl, cycloalkyl, heterocyclyl or heterocyclylalkyl.

Abstract: The excessive bit error rate detection algorithm operates in two modes: BURST mode and non-BURST mode. In non-BURST mode, an alarm state is entered if an error count exceeds a threshold within a set number of frames and exits the alarm state when the error count stays below a threshold for a set number of frames. In the BURST mode, the alarm state is not entered unless the error count exceeds the threshold two consecutive times and does not exit the alarm state unless the error rate remains below a threshold for two consecutive frame counts.

Abstract: Methods for retiming and realigning SONET signals include demultiplexing STS-1 signals from an STS-3 signal, buffering each of the three signals in a FIFO, determining the FIFO depth over time, determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. For a 28-byte deep FIFO, if the depth of a FIFO is 12-16 bytes, no pointer leaking is performed. If the depth is 0-4 bytes, an immediate positive leak is performed. If the depth is 24-28, an immediate negative leak is performed. If the depth is 5-11 bytes a calculated positive leak is performed. If the depth is 17-23 bytes, a calculated negative leak is performed. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received every 32 seconds (256,000 frames).

Abstract: The excessive bit error rate detection algorithm operates in two modes: BURST mode and non-BURST mode. In non-BURST mode, an alarm state is entered if an error count exceeds a threshold within a set number of frames and exits the alarm state when the error count stays below a threshold for a set number of frames. In the BURST mode, the alarm state is not entered unless the error count exceeds the threshold two consecutive times and does not exit the alarm state unless the error rate remains below a threshold for two consecutive frame counts.

Abstract: Methods for retiming and realigning SONET signals include demultiplexing STS-1 signals from an STS-3 signal, buffering each of the three signals in a FIFO, determining the FIFO depth over time, determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. For a 28-byte deep FIFO, if the depth of a FIFO is 12-16 bytes, no pointer leaking is performed. If the depth is 0-4 bytes, an immediate positive leak is performed. If the depth is 24-28, an immediate negative leak is performed. If the depth is 5-11 bytes a calculated positive leak is performed. If the depth is 17-23 bytes, a calculated negative leak is performed. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received every 32 seconds (256,000 frames).