Abstract: Composite foams are provided including a metal template and a conformal atomic-scale film disposed over such metal template to form a 3-dimensional interconnected structure. The metal template includes a plurality of sintered interconnects, having a plurality of first non-spherical pores, a first non-spherical porosity, and a first surface-area-to-volume ratio. The conformal atomic-scale film has a plurality of second non-spherical pores, a second non-spherical porosity, and a second surface-area-to-volume ratio approximately equal to the first surface-area-to-volume ratio. The plurality of sintered interconnects has a plurality of dendritic particles and the conformal atomic-scale film includes at least one of a layer of graphene and a layer of hexagonal boron nitride.

Abstract: An electronics chassis is provided. The electronics chassis includes a plurality of panels that define an interior space. One panel of the plurality of panels has a composite segment having an internal face and an external face. The electronics chassis further includes a conductive thermal pathway that extends through the panel from the internal face of the composite segment to the external face of the composite segment.

Abstract: A circuit card assembly is provided. The assembly includes a first printed circuit board, at least one electronic component mounted on the first printed circuit board at a predetermined location, a frame coupled to the first printed circuit board, and a heat transfer assembly coupled to the frame. The heat transfer assembly includes a first plate extending over at least a portion of the first printed circuit board, a heat pipe coupled to the first plate, and a thermally conductive member positioned between the at least one electronic component and the heat pipe. The thermally conductive member is selectively mounted at predetermined locations along the first plate based on the predetermined location of the at least one electronic component.

Abstract: A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure.

Abstract: A circuit card assembly is provided. The circuit card assembly includes a printed circuit board, at least one electronic component mounted on the printed circuit board, and a frame coupled to the printed circuit board such that the electronic component is disposed between the printed circuit board and the frame. The circuit card assembly also includes a heat transfer device coupled to the frame. The heat transfer device has a heat pipe disposed at least in part between the frame and the printed circuit board. The circuit card assembly further includes a pivotable brace biasing the heat pipe toward the electronic component to facilitate cooling the electronic component.

Abstract: An electronic device assembly includes a heat sink coupled to an electronic device to dissipate the heat produced by the electronic device. A heat spreader is coupled between the electronic device and the heat sink to transfer heat from the electronic device to the heat sink. Furthermore, at least one of the electronic device, the heat spreader, and the heat sink is disposed with a disordered carbon coating.

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract: A thermal interface device having a containment structure and a thermal conductor is provided. Further, the containment structure includes at least one wall, where the containment structure is configured to facilitate passage of heat. Furthermore, the thermal interface device includes a thermal conductor disposed at least in a portion of the containment structure. Moreover, the thermal conductor is configured to reversibly switch between a solid state and a liquid state. Also, the thermal interface device is a re-workable device.

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract: An electronics chassis is provided. The electronics chassis includes a plurality of panels that define an interior space. One panel of the plurality of panels has a composite segment having an internal face and an external face. The electronics chassis further includes a conductive thermal pathway that extends through the panel from the internal face of the composite segment to the external face of the composite segment.

Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.

Abstract: A heat exchange assembly for dissipating heat from a hot component of a circuit card is disclosed. The heat exchange assembly includes a support structure having a first support end, a second support end, and a support portion extending between the first support end and the second support end. The support structure further includes a plurality of first projections protruding from a portion of a surface of the support structure, corresponding to the support portion. Further, the heat exchange assembly includes a vapor chamber having a casing and a wick disposed within the casing. The vapor chamber is coupled to a surface of the support structure.

Abstract: A circuit card assembly is provided. The circuit card assembly includes a printed circuit board, at least one electronic component mounted on the printed circuit board, and a frame coupled to the printed circuit board such that the electronic component is disposed between the printed circuit board and the frame. The circuit card assembly also includes a heat transfer device coupled to the frame. The heat transfer device has a heat pipe disposed at least in part between the frame and the printed circuit board. The circuit card assembly further includes a pivotable brace biasing the heat pipe toward the electronic component to facilitate cooling the electronic component.

Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.

Abstract: A heat transfer device filled with a working fluid, includes a casing and a wick disposed within the casing. The wick includes a first sintered layer, a second sintered layer, and a third sintered layer. The first sintered layer is disposed proximate to an inner surface of the casing and the second sintered layer is disposed on the first sintered layer. The second sintered layer includes a first set of 3-dimensional sintered projections and a second set of 3-dimensional sintered projections disposed along a portion of the wick. Further, the third sintered layer is disposed on at least a portion of the second sintered layer. The heat transfer device includes at least one first sintered particle of the first sintered layer, which is smaller in size than at least one second pore of the second sintered layer.

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.