Abstract: A semiconductor device includes a substrate having a first surface and a second surface. A gate pad and a source pad are laterally separated from each other and both disposed on the first surface of the substrate. A drain region is disposed on the second surface of the substrate. A first trench and a second trench are disposed in the substrate and directly below the gate pad and the source pad, respectively. A conductive portion fills the first trench. A dielectric liner is disposed in the first trench and surrounds the conductive portion. A first doped region is located on two sides of the first trench. A gate electrode fills the second trench. A gate dielectric layer is disposed in the second trench and surrounds the gate electrode. A source region is located on two sides of the second trench.

Abstract: A semiconductor device includes a substrate having a first conductivity type and including a cell region and a termination region. A trench is disposed in the substrate and located in the cell region, and a gate electrode disposed in the trench. A shielding doped region having a second conductivity type is disposed in the substrate and directly below the trench. A buried guard ring having the second conductivity type is disposed in the substrate and located in the termination region. The buried guard ring and the shielding doped region are disposed at the same depth in the substrate. In addition, a junction termination extension structure having the second conductivity type is disposed in the substrate, located directly above and separated from the buried guard ring.

Abstract: A semiconductor device includes a trench in a substrate, a gate electrode in the trench, a source contact region on a first surface of the substrate, a drain contact region on a second surface of the substrate, a heavily doped region directly below the trench, and a current spreading layer in the substrate to surround the bottom of the trench and the heavily doped region. The heavily doped region has a first conductivity type, and the width of the heavily doped region is smaller than the width of the trench in a first direction. The current spreading layer has a second conductivity type and a gradual doping concentration that is gradually increased along the first direction from the heavily doped region to the outside of the current spreading layer.

Abstract: A method of forming a semiconductor device includes forming a first layer over a substrate in a deposition chamber with a first deposition cycle and forming a second layer over the substrate in the deposition chamber with a second deposition cycle. The first deposition cycle includes flowing a first process gas over the substrate and flowing a second process gas over the substrate. The second deposition cycle includes flowing a third process gas over the substrate and flowing a fourth process gas over the substrate.

Abstract: A quick releasing mechanism includes an engagement component and a releasing component. The engagement component includes an arm structure. The arm structure has an engagement part. The releasing component is movably disposed on the engagement component. The releasing component includes a pressing protrusion for selectively pressing against the arm structure. When the releasing component is moved relative to the engagement component, the pressing protrusion of the releasing component presses against the arm structure to force the engagement part to rotate relative to the releasing component.

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Abstract: A semiconductor structure including a substrate, an epitaxy layer, an electrode structure, a first sidewall doping region, a second sidewall doping region, and a bottom doping region is provided. The substrate has a first conductivity type. The epitaxy layer has a first conductivity type and is disposed on the substrate. The electrode structure is disposed in the epitaxy layer. The electrode structure extends along a first direction. The first sidewall doping region has the first conductivity type and is disposed on one side of the electrode structure. The second sidewall doping region has a second conductivity type different than the first conductivity type and is disposed on the other side of the electrode structure. The bottom doping region has the second conductivity type and is disposed under the electrode structure. The second sidewall doping region is connected to the bottom doping region.

Abstract: A semiconductor device includes a substrate having a first conductivity type, an epitaxial layer formed on the substrate, a well region extending from a top surface of the epitaxial layer into the epitaxial layer, a drift region formed in the epitaxial layer and in contact with the bottom surface of the well region, a gate structure and a conductive structure. The epitaxial layer has the first conductivity type, the well region has the second conductivity type, and the drift region has the first conductivity type. The gate structure that extends from the top surface of the epitaxial layer penetrates the well region and is in contact with the drift region. The conductive structure is formed in the drift region and disposed below the gate structure. A gate electrode of the gate structure is separated from the underlying conductive structure by the gate dielectric layer of the gate structure.

Abstract: A semiconductor device includes a substrate, an epitaxial layer on the substrate, a well region in the epitaxial layer, an insulating pillar extending into the epitaxial layer, a first doping region in the epitaxial layer and surrounding the insulating pillar, a second doping region under the first doping region, and a gate structure formed at one lateral side of the insulating pillar and extending into the epitaxial layer. The substrate and the epitaxial layer each have a first conductivity type. The well region and the first and second doping regions each have a second conductivity type. The gate structure is separated from the insulating pillar. The insulating pillar penetrates the first doping region by extending from the top portion to the bottom portion of the first doping region. The first doping region is electrically connected to the well region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, an epitaxy layer, a well region, a gate electrode, a conductive structure, and a source electrode. The substrate has a first conductive type. The epitaxy layer has the first conductive type and is disposed on the substrate. The well region has a second conductive type. The second conductive type is different than the first conductive type. The well region is disposed in the epitaxy layer. The gate electrode is disposed on the well region. The conductive structure includes an upper portion and a lower portion. The lower portion extends in the direction of the substrate into the epitaxy layer and the upper portion is disposed on the epitaxy layer. The source electrode is disposed on the conductive structure.

Abstract: A method of forming a semiconductor device includes forming a first layer over a substrate in a deposition chamber with a first deposition cycle and forming a second layer over the substrate in the deposition chamber with a second deposition cycle. The first deposition cycle includes flowing a first process gas over the substrate and flowing a second process gas over the substrate. The second deposition cycle includes flowing a third process gas over the substrate and flowing a fourth process gas over the substrate.

Abstract: Some implementations described herein provide a method. The method includes forming, in a nanostructure transistor device, a recessed portion for a source/drain region of the nanostructure transistor device. The method also includes forming an inner spacer on a bottom of the recessed portion and on sidewalls of the recessed portion. The method further includes etching the inner spacer such that the inner spacer is removed from the bottom and from first portions of the sidewalls, and such that the inner spacer remains on second portions of the sidewalls. The method additionally includes forming, after etching the inner spacer, a buffer layer over a substrate of the nanostructure transistor device at the bottom of the recessed portion. The method further includes forming the source/drain region over the buffer layer in the recessed portion.

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

Abstract: The invention relates to a lactic acid bacterium (LAB), Lactobacillus fermentum PS150, and a bioactive protein produced by the LAB, which has an advantageous effect in improving mood disorder, enhancing cognitive functions in brain and treating or preventing a neurodegenerative disease.

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.