Patents by Inventor Shan Wang

Shan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220383554
    Abstract: A method, apparatus, and non-transitory computer-readable medium for adaptive neural image compression by meta-learning using substitute QF settings, which includes generating one or more substitute quality factors via a plurality of iterations using the original quality factors, wherein the substitute quality factors are a modified version of the original quality factors and are associated with a single instance of neural network loop filtering model. The approach may further include determining a neural network based loop filter comprising neural network based loop filter parameters and a plurality of layers, wherein the neural network based loop filter parameters include shared parameters and adaptive parameters, and may further include generating enhanced video data, based on the one or more substitute quality factors and the input video data, using the neural network based loop filter.
    Type: Application
    Filed: May 11, 2022
    Publication date: December 1, 2022
    Applicant: TENCENT AMERICA LLC
    Inventors: Wei JIANG, Wei WANG, Xiaozhong XU, Shan LIU
  • Publication number: 20220385896
    Abstract: Aspects of the disclosure provide a method, an apparatus, and a non-transitory computer-readable storage medium for video decoding. The apparatus can include processing circuitry. The processing circuitry is configured to receive an image or video comprising one or more blocks. The processing circuitry can decode a first post-filtering parameter in the image or video corresponding to the one or more blocks to be reconstructed. The first post-filtering parameter applies to at least one of the one or more blocks and has been updated by a post-filtering module in a post-filtering neural network (NN) that is trained based on a training dataset. The processing circuitry can determine the post-filtering NN in a video decoder corresponding to the one or more blocks based on the first post-filtering parameter. The processing circuitry can decode the one or more blocks based on the determined post-filtering NN corresponding to the one or more blocks.
    Type: Application
    Filed: May 20, 2022
    Publication date: December 1, 2022
    Applicant: Tencent America LLC
    Inventors: Ding DING, Wei JIANG, Wei WANG, Shan LIU
  • Patent number: 11504812
    Abstract: A method for making an infrared light absorber is provided, and the method includes following steps: providing a first carbon nanotube array on a substrate; truncating the carbon nanotube array by irradiating a top surface of the carbon nanotube array by a laser beam in two directions, the top surface being away from the substrate, wherein the two directions being at an angle, the angle is in a range of 30 degrees to 90 degrees.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 22, 2022
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ying-Cheng Wang, Zhong-Zheng Huang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Publication number: 20220368918
    Abstract: Aspects of the disclosure provide a method and an apparatus for video encoding. The apparatus includes processing circuitry configured to perform an iterative update of sample values of a plurality of samples in an initial input image. The iterative update includes generating a coded representation of a final input image based on the final input image by an encoding neural network (NN) and at least one training module. The final input image has been updated from the initial input image by a number of iterations of the iterative update. The iterative update includes generating a reconstructed image of the final input image based on the coded representation of the final input image by a decoding NN. One of a rate-distortion loss for the final input image or the number of iterations of the iterative update satisfies a pre-determined condition. An encoded image corresponding to the final input image is generated.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 17, 2022
    Applicant: Tencent America LLC
    Inventors: Ding DING, Wei JIANG, Wei WANG, Shan LIU
  • Publication number: 20220366117
    Abstract: A method of making a semiconductor structure includes forming a plurality of gate electrodes over a plurality of active regions. The method further includes increasing a width of a portion of each of the plurality of gate electrodes between adjacent active regions of the plurality of active regions, wherein increasing the width of the portion of each of the plurality of gate electrodes comprises increasing the width of less than an entirety of each of the plurality of gate electrodes between the adjacent active regions. The method further includes removing a central region of each of the plurality of gate electrodes, wherein the central region has the increased width, and removing the central region comprises removing less than an entirety of the portion of each of the plurality of gate electrodes.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Yu-Jen CHEN, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Patent number: 11498519
    Abstract: A smart alarm module includes a connector terminal adapted to provide not more than five conductive paths from a fused box and an audio device of the vehicle to the smart alarm module, a CAN bus interface adapted to make connection to the CAN bus of the vehicle to detect communication protocol, a microcontroller adapted to arm the smart alarm module in response to the information received from the remote controller to provide the smart alarm module judgment operation based on the received information, a sensor adapted to quantized shock waves applied to the vehicle and to feed a first activating signal to the microprocessor when the quantized values exceeds a predetermined value, a power supply regulator providing power to the CAN bus interface, microprocessor, and sensor of the smart alarm module, and an output interface adapted to sound the audio device in response to output signal from the microprocessor.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: November 15, 2022
    Inventor: Reng-Shan Wang
  • Patent number: 11503323
    Abstract: A method of performing inter-picture prediction of a current picture of a video sequence is performed by at least one processor and includes determining whether the current picture uses a virtual reference picture, and based on the current picture being determined to use the virtual reference picture, generating, for the current picture, the virtual reference picture from neighboring reference pictures that are nearest neighbors to the virtual reference picture, storing the generated virtual reference picture in a decoded picture buffer, and adding the generated virtual reference picture to an active reference picture list. The method further includes performing the inter-picture prediction of the current picture, based on the active reference picture list to which the virtual reference picture is added.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: November 15, 2022
    Assignee: TENCENT AMERICA LLC
    Inventors: Byeongdoo Choi, Zeqiang Li, Wei Wang, Xiaozhong Xu, Shan Liu
  • Publication number: 20220357377
    Abstract: The application provides an apparatus, a system, a detector and a method. The apparatus includes: a power supply voltage detector, including: N buffers, an input terminal of a first buffer being connected to a clock signal, output terminals of other buffers being connected to the input terminal of an adjacent buffer; N latch chains, each of which includes M latches, a clock input terminal of each latch being connected to a clock signal, a D terminal of a first latch of each latch chain being connected to the output terminal of a corresponding buffer, Q terminals of other latches being connected to the D terminal of an adjacent latch, M and N being positive integers, the D terminal of each latch being connected to an area where a power supply voltage is to be detected; and a voltage regulation module connected to the Q terminal of each latch.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 10, 2022
    Inventors: Junmou ZHANG, Dongrong ZHANG, Shan LU, Jian WANG
  • Publication number: 20220357215
    Abstract: Disclosed are a temperature measurement circuit and method. The circuit includes a first temperature sensing circuit, a second temperature sensing circuit and a data processing unit. The first temperature sensing circuit is configured to generate a first measurement signal for characterizing a temperature based on an inputted first current signal, a magnitude of the first current signal being correlated to temperature. The second temperature sensing circuit is configured to generate a second measurement signal for characterizing the temperature based on an inputted second current signal, the second current signal being independent of temperature. The data processing unit is configured to determine a current temperature based on a first characteristic parameter corresponding to the first measurement signal and a second characteristic parameter corresponding to the second measurement signal.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 10, 2022
    Inventors: Chuang ZHANG, Shan LU, Junmou ZHANG, Yimin CHEN, Jian WANG, Yuanlin CHENG
  • Publication number: 20220357924
    Abstract: A circuit module for performing matrix multiplication and a method for performing matrix multiplication are provided. The circuit module includes a row-column calculation unit for performing a row-column multiplication calculation. The row-column calculation unit includes a multiplication unit and an addition unit. The multiplication unit is configured to perform a multiplication calculation based on a row matrix element of a first matrix and a column matrix element of a second matrix, and receive at least one electrical signal sequentially inputted in multiple predetermined timing sequences via an input end of the multiplication unit. The electrical signal represents the row matrix element of the first matrix. The addition unit is configured to accumulate a product, obtained by the multiplication unit based on the inputted electrical signal, to perform the row-column multiplication calculation.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 10, 2022
    Inventors: Chuang ZHANG, Shan LU, Junmou ZHANG, Yimin CHEN, Yuanlin CHENG, Jian WANG
  • Publication number: 20220358184
    Abstract: A matrix multiplication circuit module and a matrix multiplication method are provided by the embodiments of the present disclosure. The circuit module includes one or more row-column calculation units for realizing row-column multiplication calculation. Each of the row-column calculation units comprises one or more multiplying units and an adding unit. Each of the one or more multiplying unit has an output end connected to an input end of the adding unit. Each of the multiplying units comprises an electrical signal regulating subunit and a load. The electrical signal regulating subunit is configured to regulate a magnitude of an input electrical signal. A multiplication operation is performed by the electrical signal regulating subunit and the load in response to an electrical signal inputted to the multiplying unit. The load has a fixed load value.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 10, 2022
    Inventors: Chuang ZHANG, Shan LU, Junmou ZHANG, Yimin CHEN, Jian WANG, Yuanlin CHENG
  • Publication number: 20220358071
    Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 10, 2022
    Inventors: Yimin CHEN, Shan LU, Chuang ZHANG, Junmou ZHANG, Yuanlin CHENG, Jian WANG
  • Publication number: 20220358078
    Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 10, 2022
    Inventors: Yimin CHEN, Shan LU, Junmou ZHANG, Chuang ZHANG, Yuanlin CHENG, Jian WANG
  • Publication number: 20220360770
    Abstract: Aspects of the disclosure provide a method, an apparatus, and a non-transitory computer-readable storage medium for video decoding. The apparatus can include processing circuitry. The processing circuitry is configured to reconstruct blocks of an image from a coded video bitstream. The processing circuitry can perform post-processing on one of a plurality of regions of first two neighboring reconstructed blocks of the reconstructed blocks with at least one post-processing neural network (NN). The first two neighboring reconstructed blocks have a first shared boundary and include a boundary region having samples on both sides of the first shared boundary. The plurality of regions of the first two neighboring reconstructed blocks includes the boundary region and non-boundary regions that are outside the boundary region. The one of the plurality of regions is replaced with the post-processed one of the plurality of regions of the first two neighboring reconstructed blocks.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 10, 2022
    Applicant: Tencent America LLC
    Inventors: Ding DING, Wei JIANG, Wei WANG, Shan LIU
  • Publication number: 20220357370
    Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 10, 2022
    Inventors: Junmou ZHANG, Shan LU, Chuang ZHANG, Yimin CHEN, Jian WANG, Yuanlin CHENG
  • Publication number: 20220360267
    Abstract: Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.
    Type: Application
    Filed: June 19, 2020
    Publication date: November 10, 2022
    Inventors: Jun LIU, Zhaobi WEI, Shan WANG, Pei DUAN, Mengbi LEI
  • Patent number: 11496151
    Abstract: An apparatus of neural network model decompression includes processing circuitry. The processing circuitry can be configured to receive, from a bitstream of a compressed neural network representation, one or more first syntax elements associated with a 3-dimensional coding unit (CU3D) partitioned from a 3-dimensional coding tree unit (CTU3D). The first CTU3D can be partitioned from a tensor in a neural network. The one or more first syntax elements can indicate that the CU3D is partitioned based on a 3D pyramid structure that includes multiple depths. Each depth corresponds to one or more nodes. Each node has a node value. Second syntax elements corresponding to the node values of the nodes in the 3D pyramid structure can be received from the bitstream in a breadth-first scan order for scanning the nodes in the 3D pyramid structure. Model parameters of the tensor can be reconstructed based on the received second syntax elements.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: November 8, 2022
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Wang, Wei Jiang, Shan Liu
  • Patent number: 11496775
    Abstract: A method, computer program, and computer system is provided for compressing a neural network model. One or more coding tree units are identified corresponding to a multi-dimensional tensor associated with a neural network. A set of weight coefficients associated with the coding tree units is unified. A model of the neural network is compressed based on the unified set of weight coefficients.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 8, 2022
    Assignee: TENCENT AMERICA LLC
    Inventors: Wei Jiang, Wei Wang, Shan Liu
  • Patent number: 11494926
    Abstract: A method for performing hybrid depth detection with aid of an adaptive projector and associated apparatus are provided. The method includes: utilizing an image processing circuit to obtain distance information; utilizing the image processing circuit to determine a distance range according to the distance information; utilizing the image processing circuit to perform projection type selection to determine at least one selected projection type corresponding to the distance range among multiple predetermined projection types; utilizing the adaptive projector to perform projection of the at least one selected projection type to capture at least one corresponding image with a camera, and utilizing the image processing circuit to perform depth detection according to corresponding image to generate depth map; and utilizing the image processing circuit to selectively output the depth map as resultant depth map or perform depth data combination to generate combined depth map as resultant depth map.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: November 8, 2022
    Assignees: HIMAX TECHNOLOGIES LIMITED, LIQXTAL TECHNOLOGY INC.
    Inventors: Biing-Seng Wu, Pen-Hsin Chen, Ching-Wen Wang, Cheng-Che Tsai, Hung-Shan Chen, Yi Hung, Ming-Syuan Chen, Hsueh-Tsung Lu, Wu-Feng Chen
  • Publication number: 20220353528
    Abstract: Aspects of the disclosure provide a method, an apparatus, and a non-transitory computer-readable storage medium for video decoding. The apparatus can include processing circuitry. The processing circuitry is configured to decode first neural network update information in a coded bitstream for a first neural network in the video decoder. The first neural network is configured with first pretrained parameters. The first neural network update information corresponds to a first block in an image to be reconstructed and indicates a first replacement parameter corresponding to a first pretrained parameter in the first pretrained parameters. The processing circuitry is configured to update the first neural network in the video decoder based on the first replacement parameter. The processing circuitry can decode the first block based on the updated first neural network for the first block.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 3, 2022
    Applicant: Tencent America LLC
    Inventors: Ding DING, Wei JIANG, Wei WANG, Shan LIU