Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to form air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etch process to form recesses between metal interconnects formed on a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize the critical dimension (CD) dependent etching provided by wet etch processes to etch an intermetal dielectric material formed between the metal interconnects at a faster rate than the intermetal dielectric material is etched in surrounding areas of the patterned substrate. This enables the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between the metal interconnects without using a dry etch process.

Abstract: A method of encoding includes receiving a polygon mesh comprising a plurality of original vertices. The method further includes deriving an initial base mesh from the polygon mesh, the initial base mesh including a first set of base mesh vertices. The method further includes performing a symmetrize process on the initial base mesh to generate a symmetrical base mesh that includes a first side having the first set of base mesh vertices and a second side having a second set of base mesh vertices, each base mesh vertex in the first set of base mesh vertices having a corresponding symmetric vertex in the second set of base mesh vertices. The method further includes determining a first displacement between each original vertex in the polygon mesh located on the second side of the symmetrical base mesh and a nearest vertex included in the second set of base mesh vertices.

Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to control fin height and channel area in a fin field effect transistor (FinFET) having gaps of variable CD. More specifically, the present disclosure provides improved transistor fabrication processes and methods that utilize a wet etch process, instead of a dry etch process, to remove the oxide material deposited within the gaps formed between the fins of a FinFET. By utilizing a wet etch process, the improved transistor fabrication processes and methods described herein provide a means to adjust or individually control the fin height of one or more the fins, thereby providing greater control over the channel area of the FinFET.

Abstract: A method and apparatus comprising computer code configured to cause a processor or processors to obtain volumetric data of at least one three-dimensional (3D) visual content, derive a mesh from a frame of the volumetric data, the mesh including a plurality of base mesh vertices, determine a displacement of at least one vertex, that is not of the base mesh vertices, based on a series of projections from at least one of the plurality of base mesh vertices that is a neighboring one of the plurality of base mesh vertices to the at least one vertex, predicting the at least one vertex based at least on the determined displacement, and encode the volumetric data based on the predicted at least one vertex.

Abstract: Methods and systems for emulating a hardware accelerator is provided. When executed by a computer, the platform includes a plurality of computational resources provided by the computer; a hardware emulator operated on a first computational resource of the plurality of computational resources; and an accelerator being emulated in the platform and operated on a second computational resource of the plurality of computational resources, the accelerator being configured to execute an offloading operation.

Abstract: Embodiments of a wet etch process and method are disclosed to provide uniform etching of material formed within features (such as, e.g., trenches, holes, slits, etc.) having different critical dimension (CD). By combining a non-aqueous organic-based etch solution and an aqueous-based etch solution (either in series or in parallel) within a wet etch process, the disclosed embodiments utilize the opposing effects of CD-dependent etching to provide uniform etching of the material, regardless of CD.

Abstract: Method, apparatus, and system for texture coordinate prediction for mesh compression are provided. The process may include receiving, for a mesh, a coordinate of a first vertex and a coordinate of a prediction candidate vertex in a three dimensional (3D) space. The process may include determining a stretch perpendicular distance associated with the first vertex and the prediction candidate vertex, the stretch perpendicular distance being based on a conversion of the 3D space into a two dimensional (2D) space, and determining a 2D texture coordinate of the first vertex based on the stretch perpendicular distance associated with the first vertex and the prediction candidate vertex. The process may also include determining a residual of a predicted coordinate of the first vertex and an actual 2D coordinate of the first vertex; and compressing the mesh based on entropy coding the residual.

Abstract: Aspects of the disclosure provide methods and apparatuses for mesh coding (e.g., compression and decompression). In some examples, an apparatus for mesh coding includes processing circuitry. The processing circuitry decodes a plurality of initial maps in two-dimension from a bitstream carrying a three-dimensional (3D) mesh frame. The processing circuitry determines at least two sampling rates associated with different portions of the plurality of initial maps and recovers from the plurality of initial maps and based on the at least two sampling rates associated with the different portions of the plurality of initial maps to obtain a plurality of recovered maps. A first portion of the plurality of initial maps is recovered based on a first sampling rate, and a second portion of the plurality of initial maps is recovered based on a second sampling rate. The processing circuitry reconstructs the 3D mesh frame based on the plurality of recovered maps.

Abstract: A processing circuitry decodes a plurality of maps in 2D from a bitstream carrying a mesh frame. The mesh frame represents a surface of an object with polygons. The plurality of maps includes a decoded geometry map and a decoded attribute map with an adaptive 2D atlas sampling applied. The processing circuitry determines at least a first sampling rate and a second sampling rate according to syntaxes signaled in the bitstream. The first sampling rate is applied to a first region of the mesh frame and the second sampling rate is applied to a second region of the mesh frame during the adaptive 2D atlas sampling. The processing circuitry reconstructs, based on the plurality of maps, at least a first vertex of the mesh frame according to the first sampling rate, and a second vertex of the mesh frame according to the second sampling rate.

Abstract: Provided is a siRNA for inhibiting HBV gene expression, including a sense strand and an antisense strand. The sense strand includes a nucleotide sequence 1, and the antisense strand includes a nucleotide sequence 2; the nucleotide sequence 1 and the nucleotide sequence 2 are at least partially reversely complementary to form a double-stranded region; the nucleotide sequence 1 and the nucleotide sequence shown in SEQ ID NO: 1 are equal in length, and no more than 3 nucleotide differences are generated; the nucleotide sequence 2 and the nucleotide sequence shown in SEQ ID NO: 2 are equal in length, and no more than 3 nucleotide differences are generated; nucleotides of the 7th, 8th, and 9th bits of the nucleotide sequence 1 and the 2nd, 6th, 14th, and 16th of the nucleotide sequence 2 are fluoro-modified nucleotides. Also provided are a pharmaceutical composition and a conjugate containing the siRNA.

Abstract: A method of point cloud geometry encoding includes receiving a slice of a point cloud frame for encoding, and constructing an octree representing a geometry of points in a bounding box of the slice where a current node of the octree is partitioned with a quadtree (QT) partition or a binary tree (BT) partition. The constructing includes determining a value of a partitionSkip variable specifying a partition type and a partition direction of the current node of the octree.

Abstract: A computer-implemented method according to one embodiment includes generating a first matrix based on words extracted from documents, and generating a second matrix based on deduplication chunks. The deduplication chunks include words of the documents. Word clustering is performed based on an analysis performed on the second matrix. Each cluster of the words represents a feature of at least one of the documents. The method further includes generating a third matrix based on the first matrix and the clusters, and performing text mining using the third matrix. A computer program product according to another embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.

Abstract: Coding information of a mesh is received. The coding information includes a plurality of first coordinates and a plurality of second coordinates corresponding to a plurality of vertices and a texture map that are associated with the mesh. A respective first coordinate and a respective second coordinate associated with each of the plurality of vertices are normalized by adjusting the respective first coordinate based on a first factor and the respective second coordinate based on a second factor. The first factor and the second factor are associated with at least one of (i) a bit depth value indicating a coded range of the first coordinates and the second coordinates and (ii) a size of the texture map. The normalized respective first coordinate and the normalized respective second coordinate are expanded based on the first factor and the second factor respectively.

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: A semiconductor tester and a method for calibrating a probe card and a device under testing (DUT) are disclosed. The semiconductor tester includes: a support platform, including a support surface and configured to be able to move along a direction parallel to the support surface and rotate around a rotating shaft perpendicular to the support surface; a probe card including a plurality of probes stretching towards the support platform; and an alignment assembly, including: at least two first laser emitting apparatuses emitting a plurality of first laser beams; and a second laser emitting apparatus emitting a plurality of second laser beams. The first laser beams and the second laser beams are perpendicular to each other and are each arranged sequentially along a direction perpendicular to the support surface. The semiconductor tester aligns a probe card to a DUT with improved accuracy, thereby preventing the damage to the probe card.

Abstract: This document describes systems and techniques related to deep association for sensor fusion. For example, a model trained using deep machine learning techniques, may be used to generate an association score matrix that includes probabilities that tracks from different types of sensors are related to the same objects. This model may be trained using a convolutional recurrent neural network and include constraints not included in other training techniques. Focal loss can be used during training to compensate for imbalanced data samples and address difficult cases, and data expansion techniques can be used to increase the multi-sensor data space. Simple thresholding techniques can be applied to the association score matrix to generate an assignment matrix that indicates whether tracks from one sensor and tracks from another sensor match. In this manner, the track association process may be more accurate than current sensor fusion techniques, and vehicle safety may be increased.

Abstract: A method of manufacturing thin film transistor(s) includes: providing a monocrystalline silicon wafer, the monocrystalline silicon wafer including a first surface and a second surface that are opposite to each other; forming a bubble layer between the first surface and the second surface of the monocrystalline silicon wafer, the bubble layer dividing the monocrystalline silicon wafer into two portions arranged side by side in a direction perpendicular to the second surface, and a portion of the monocrystalline silicon wafer that is located between the bubble layer and the second surface being a monocrystalline silicon film having a target thickness; providing a substrate, and transferring the monocrystalline silicon film onto the substrate by breaking the monocrystalline silicon wafer at the bubble layer; and patterning the monocrystalline silicon film transferred to the substrate to form active layer(s) of the thin film transistor(s).

Abstract: -- The present disclosure relates to an IGBT driving circuit and a power conversion device. The IGBT driving circuit includes a driving chip with a first driving signal port (Vo); a driving resistor adjustment circuit connected between the first driving signal port (Vo) and a gate (G) of an IGBT, a driving resistor formed by the driving resistor adjustment circuit being adjustable in size; a peak voltage detection circuit connected to the gate (G) of the IGBT which is conductive to the first driving signal port (Vo), the peak voltage detection circuit being configured to monitor whether a peak voltage occurs when the IGBT is turned off; and a resistor adjustment control circuit connected between the peak voltage detection circuit and the driving resistor adjustment circuit and configured to reduce a resistor formed by the driving resistor adjustment circuit when the peak voltage is monitored when the IGBT is turned off.

Abstract: This document describes systems and techniques for determining a height of an object in a surrounding of a vehicle. In a first aspect, the systems and techniques include acquiring radar data for each of a plurality of vertically distributed antenna elements of a radar antenna. In additional aspects, the systems and techniques include estimating an elevation spectrum from the acquired radar data, extracting one or more features representative of the shape of the estimated elevation spectrum, and determining the height of the object using the extracted one or more features.