Abstract: A packaging substrate structure with a semiconductor chip embedded therein is disclosed, including a carrier board having a first and an opposed second surfaces and disposed with at least a through cavity; a semiconductor chip received in the through cavity, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is disposed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are disposed on surfaces of the electrode pads; a buffer layer disposed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer disposed on the buffer layer; and a first circuit layer disposed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures disposed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expa

Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and a build-up structure mounted on the surface of the aluminum plate, the active surface of the chip, and the surface of the electrode pad, wherein the build-up structure comprises at least one conducting to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed. Therefore, the plate structure having a chip embedded therein can be processed by a simple method to achieve the tenacity of aluminum and the rigidity of aluminum oxide.

Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract: The present invention relates to a package on package (PoP) structure, which comprises: a first packaging substrate having a plurality of conductive elements on its surface; a second packaging substrate having a plurality of conductive elements on its surface; and a surface-ceramic aluminum plate sandwiched between the first packaging substrate and the second packaging substrate. The surface-ceramic aluminum plate includes plural plated through holes extending through the layer. In addition, the first packaging substrate electrically conducts with the second packaging substrate through these plated through holes. The disclosed structure eliminates the warpage problem of PoP structure, and enhances the strength of PoP structure.

Abstract: The present invention relates to a packaging substrate structure having an semiconductor chip embedded therein and a method for manufacturing the same. The structure comprises: a substrate body having a through cavity, wherein the substrate body is a multilayer board which comprises a core board and a first built-up structure disposed on each of the opposite surfaces of the core board; an semiconductor chip disposed and fixed in the cavity, wherein the active surface of the semiconductor chip has a plurality of electrode pads thereon; and a second built-up structure disposed on at least one surface of the substrate body as well as the surface of the semiconductor chip, wherein the second built-up structure has a plurality of conductive vias conducting to the first built-up structure. The present invention can reduce the stress imposed on the surface of the semiconductor chip and increase the reliability of the whole package structure.

Abstract: A packaging substrate having a chip embedded therein, comprises a first aluminum substrate having a first cavity therein; a second aluminum substrate having a second cavity corresponding to the first cavity; a dielectric layer disposed between the first aluminum substrate and the second aluminum substrate; a chip embedded in the first cavity and the second cavity, having an active surface with a plurality of electrode pads thereon; and one built-up structure disposed on the surface of the first aluminum substrate and the active surface of the chip, wherein the built-up structure has a plurality of conductive vias electrically connecting to the electrode pads. The substrate warpage is obviously reduced by the assistance of using aluminum or aluminum alloy as the material of the substrate. Also, a method of manufacturing a packaging substrate having a chip embedded therein is disclosed.

Abstract: A semiconductor chip is disclosed, which comprises a chip having an active surface; plural electrode pads disposed on the active surface of the chip; a first passivation layer disposed on the chip, which has openings corresponding to the electrode pads to expose the electrode pads, wherein the first passivation layer is made of a material having high alkali resistance and low coefficient of elasticity; and plural metal bumps disposed in the openings of the first passivation layer. Therefore, as forming the metal bumps by a chemical deposition technique, the damage to the passivation layer can be prevented. Besides, as the semiconductor chip is embedded in a package structure, the problem of delamination occurred due to the mismatch in the coefficients of thermal expansion of the semiconductor chip and the dielectric layers can be avoided. Accordingly, the yield of the package structure having the semiconductor chip embedded therein can be improved.

Abstract: A semiconductor chip embedding structure is disclosed, including a carrier board having a first and an opposed second surfaces and formed with at least a through hole; a semiconductor chip received in the through hole, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is formed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are formed on surfaces of the electrode pads; a buffer layer formed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer formed on the buffer layer; and a first circuit layer formed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures formed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the

Abstract: A carrier plate structure having a chip embedded therein, comprises an aluminum plate having plural through-holes extending from the upper surface to the lower surface of the aluminum plate, a cavity therein, and an aluminum oxide layer formed on the surface of the aluminum plate; a chip embedded in the cavity with an active surface having plural electrode pads set thereon; and at least one build-up structure mounted on the surface of the aluminum plate and the active surface of the chip, wherein the build-up structure comprises at least one conductive structure to electrically connecting to the electrode pad. Besides, a method of manufacturing a carrier plate structure having a chip embedded therein is disclosed.

Abstract: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and a build-up structure mounted on the surface of the aluminum plate, the active surface of the chip, and the surface of the electrode pad, wherein the build-up structure comprises at least one conducting to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed. Therefore, the plate structure having a chip embedded therein can be processed by a simple method to achieve the tenacity of aluminum and the rigidity of aluminum oxide.

Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

Abstract: The invention provides a method for fabricating printed circuit board having an embedded semiconductor chip, including: providing a carrier board including a first and a second surface and at least one through hole penetrating the first and second surfaces; disposing a semiconductor chip in the through hole and including an active surface and an inactive surface, the active surface including a plurality of electrode pads; forming at least one non photoimagable laminating layer on the first surface of the carrier board with a through hole to expose the inactive surface of the semiconductor chip; forming a dielectric layer on the second surface of the carrier board and the active surface of the semiconductor chip; and forming a circuit layer on the dielectric layer, the circuit layer electrically connecting to the electrode pads of the semiconductor chip through conductive structures in the dielectric layer, thereby preventing the carrier board from warpage due to temperature variations and an asymmetric struct

Abstract: The invention provides a printed circuit board having an embedded semiconductor chip, includes: a carrier board having a first and an opposing second surface and a through hole penetrating the first and second surfaces; a semiconductor chip disposed in the through hole and having an active surface and an inactive surface, wherein the active surface includes a plurality of electrode pads; at least one non photoimagable laminating layer formed on the first surface of the carrier board and with a through hole to expose the inactive surface of the semiconductor chip; a dielectric layer and a circuit layer formed on the second surface of the carrier board and the active surface of the semiconductor chip, wherein the circuit layer electrically connects to the electrode pads of the semiconductor chip, thereby preventing the carrier board from warpage due to temperature variations and an asymmetric structure during a single-side circuit formation process of the carrier board.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

Abstract: A circuit board structure with an embedded semiconductor chip and a fabrication method thereof are provided, including the steps of providing a semiconductor wafer having an active surface with a plurality of electrode pads, a connection metal layer formed on the electrode pads: forming a protective layer on the connection metal layer and the semiconductor wafer, performing a cutting process to form a plurality of semiconductor dies, providing a carrier board having at least on e cavity for receiving the semiconductor chip; and forming sequentially on the protective layer covering the semiconductor chip and the carrier board a dielectric layer and a circuit layer electrically connected to the connection metal layer of the semiconductor chip. The present invention is a simple, in process and low in process cost, due to the connection metal layer covered by the protective layer formed on the semiconductor chip protected from oxidation and contamination.

Abstract: A plate structure having a chip embedded therein, comprises an aluminum oxide plate having an upper surface, a lower surface, plural aluminum channels connected to the upper surface and the lower surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and at least one build-up structure mounted on the surface of the aluminum oxide plate and the active surface of the chip, wherein the build-up structure comprises at least one conductive structure to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed.

Abstract: A carrier board structure with a semiconductor chip embedded therein and a method for fabricating the same are proposed. A rectangular cavity is formed at a predetermined position of the carrier board, and at least a breach is formed at a corner of the rectangular cavity, wherein the breach is composed of a plurality of drilling holes. Thus, the breach is capable of providing the rectangular cavity with a larger space for receiving a semiconductor chip in the rectangular cavity, when in the process of disposing the semiconductor chip into the rectangular cavity.