Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract: An organic electroluminescent panel having a silver alloy is disclosed, which has a substrate; a plurality of the first electrodes; a plurality of the second electrodes; a plurality of conducting lines containing a silver alloy; a plurality of isolating walls; and a plurality of organic electroluminescent media. The first electrodes are arranged in parallel on the substrate. The organic electroluminescent media are disposed on the first electrodes. The second electrodes are disposed on the organic electroluminescent media. The conducting lines containing the silver alloy connect to the first electrodes or the second electrodes. The silver alloy contained in the conducting lines has 80 to 99.8 mol % of silver; 0.1 to 10 mol % of copper; and 0.1 to 10 mol % of at least one transition metal selected from the group consisting of palladium (Pd), magnesium (Mg), gold (Au), platinum (Pt), and the combinations thereof.

Abstract: A semiconductor device with electroless plating metal connecting layer and a method for fabricating the same are proposed. A supporting board with at least one cavity is provided. At least one semiconductor chip with a plurality of copper electrode pads is received in the cavity and an insulating protecting layer is formed on the semiconductor chip. A plurality of holes is formed in the insulating protecting layer to expose the copper electrode pads. An electroless plating metal connecting layer is formed on the copper electrode pads by electroless plating. Therefore, the electrically connecting process of the semiconductor chip is simplified and easily practiced, and the fabrication cost is reduced.

Abstract: A method for reading an IC tag concealing part of data of the present invention includes steps of: the IC tag receiving a signal transmitted by a reader through an antenna (the frequency of the signal is 13.56MHz, 433.92MHz, 860M˜930MHz (UHF), 2.45GHz, 5.

Abstract: A high performance Radio Frequency Identification (RFID) system and the operating method thereof. The RFID system includes a reader, a plurality of passive tags, and at least one local reader to communicate with nearby passive tags and further forward results to the reader. A repeater tag or a semi-active tag can serve as a local reader. An operating method of the high performance RFID system, a repeater tag operating method, a semi-active tag electric power detecting method, and an operating method for searching for no electric power tags are further provided.

Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

Abstract: A package structure of an OEL panel includes a printed circuit board, at least one OEL panel, and several bumps. Wherein, the OEL panel has several poly solder interconnections arranged in an array structure. The printed circuit board has several solder pads, which are also implemented with bumps. The at least one OEL panel is disposed on the printed circuit board to have the electric connection with the printed circuit board through the poly solder interconnections and the bumps.

Abstract: A process of packaging an OEL panel is disclosed. A printed circuit board is provided, wherein the printed circuit board comprises a plurality of bonding pads and a plurality of bumps on the bonding pads. Next, at least one OEL panel having a plurality of polysolder interconnections is provided. Next, the OEL panel disposed on the printed circuit board. A reflow process is performed so that the OEL panel can electrically connect with the PCB by the polysolder interconnections. Because of the low-temperature reflow process, the process of packaging an OEL panel can be accomplished by a low temperature process.

Abstract: A package structure of an OEL panel includes a printed circuit board, at least one OEL panel, and several bumps. Wherein, the OEL panel has several poly solder interconnections arranged in an array structure. The printed circuit board has several solder pads, which are also implemented with bumps. The at least one OEL panel is disposed on the printed circuit board to have the electric connection with the printed circuit board through the poly solder interconnections and the bumps.

Abstract: An organic electroluminescent panel having a silver alloy is disclosed, which has a substrate; a plurality of the first electrodes; a plurality of the second electrodes; a plurality of conducting lines containing a silver alloy; a plurality of isolating walls; and a plurality of organic electroluminescent media. The first electrodes are arranged in parallel on the substrate. The organic electroluminescent media are disposed on the first electrodes. The second electrodes are disposed on the organic electroluminescent media. The conducting lines containing the silver alloy connect to the first electrodes or the second electrodes. The silver alloy contained in the conducting lines has 80 to 99.8 mol % of silver; 0.1 to 10 mol % of copper; and 0.1 to 10 mol % of at least one transition metal selected from the group consisting of palladium (Pd), magnesium (Mg), gold (Au), platinum (Pt), and the combinations thereof.

Abstract: A process of packaging an OEL panel is disclosed. A printed circuit board is provided, wherein the printed circuit board comprises a plurality of bonding pads and a plurality of bumps on the bonding pads. Next, at least one OEL panel having a plurality of polysolder interconnections is provided. Next, the OEL panel disposed on the printed circuit board. A reflow process is performed so that the OEL panel can electrically connect with the PCB by the polysolder interconnections. Because of the low-temperature reflow process, the process of packaging an OEL panel can be accomplished by a low temperature process.