Patents by Inventor Shao-Chang Huang

Shao-Chang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220285932
    Abstract: A protection circuit including a detection circuit, a current discharge element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect ESD events. In response to an ESD event, the detection circuit sets the detection signal to a predetermined level. The current discharge element is coupled between the first and second pads. In response to the detection signal being at the predetermined level, the current discharge element is turned on so that the ESD current passes through the current discharge element. The first transistor is coupled between a core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. In response to the detection signal being at the predetermined level, the second transistor is turned on to turn off the first transistor.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 8, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Yeh-Ning JOU, Hwa-Chyi CHIOU, Ching-Ho LI
  • Publication number: 20220278252
    Abstract: A light-emitting diode (LED) chip includes a substrate and an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer that are sequentially disposed on the substrate in such order. The second semiconductor layer has a light-emitting surface that is opposite to the active layer and that is formed with a microstructure. The microstructure includes a plurality of first protrusions that are separately disposed on the light-emitting surface, and a plurality of second protrusions that are disposed on the first protrusions and on the light-emitting surface between any two adjacent ones of the first protrusions.
    Type: Application
    Filed: February 22, 2022
    Publication date: September 1, 2022
    Inventors: Poyang CHANG, Linrong CAI, Shao-Hua HUANG, Liqin ZHU, Shuangliang LIU
  • Publication number: 20220232694
    Abstract: Provided is a circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate is disposed between the second substrate and the fourth substrate. The third substrate has an opening penetrating the third substrate and includes a first dielectric layer filling the opening. The conductive via structure penetrates the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate, and is electrically connected to the first substrate and the fourth substrate to define a signal path. The first substrate, the second substrate, the third substrate and the fourth substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.
    Type: Application
    Filed: October 8, 2021
    Publication date: July 21, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Chih-Chiang Lu, Heng-Ming Nien, Ching-Sheng Chen, Ching Chang, Ming-Ting Chang, Chi-Min Chang, Shao-Chien Lee, Jun-Rui Huang, Shih-Lian Cheng
  • Publication number: 20220223465
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.
    Type: Application
    Filed: January 12, 2021
    Publication date: July 14, 2022
    Inventors: Hsin-Yen HUANG, Ting-Ya LO, Shao-Kuan LEE, Chi-Lin TENG, Cheng-Chin LEE, Hsiaokang CHANG, Shau-Lin SHUE
  • Patent number: 11387649
    Abstract: An operating circuit is provided. A first N-type transistor determines whether to create an open circuit between a core circuit and a ground terminal according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific node according to the first detection signal.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Chun-Chih Chen, Kai-Chieh Hsu, Chih-Hsuan Lin, Yu-Kai Wang
  • Patent number: 11196249
    Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: December 7, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning Jou, Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Hwa-Chyi Chiou
  • Patent number: 11164979
    Abstract: A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 2, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Kai-Chieh Hsu, Chun-Chih Chen, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Gong-Kai Lin, Yeh-Ning Jou, Chien-Hsien Song, Hsiao-Ying Yang, Chien-Chi Hsu, Fu-Chun Tseng
  • Publication number: 20210328425
    Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 21, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning JOU, Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Hwa-Chyi CHIOU
  • Patent number: 11121212
    Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 14, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Cheng-Hsin Chuang, Shao-Chang Huang
  • Patent number: 11088541
    Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 10, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Jia-Rong Yeh, Yeh-Ning Jou, Hsien-Feng Liao, Yi-Han Wu, Chih-Cherng Liao, Chieh-Yao Chuang, Wei-Shung Chen, Ching-Wen Chen, Pang-Chuan Chen
  • Patent number: 11043486
    Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 22, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan Lin, Shao-Chang Huang, Jia-Rong Yeh, Yeh-Ning Jou, Hwa-Chyi Chiou
  • Publication number: 20210125943
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Yu-Kai WANG, Karuna NIDHI, Hwa-Chyi CHIOU
  • Publication number: 20210075215
    Abstract: An operating circuit is provided. A first N-type transistor determines whether to turn the path between a core circuit and a ground terminal on or off according to the voltage level of a specific node. An electrostatic discharge (ESD) protection circuit is coupled between an input/output pad and the core circuit to prevent an ESD current from passing through the core circuit. The ESD protection circuit includes a detection circuit and a releasing element. The detection circuit determines whether there is an ESD event at the input/output pad and generates a first detection signal according to the detection of the ESD event at the input/output pad. The releasing element provides a release path according to the first detection signal to release the ESD current. A control circuit controls the voltage level of the specific circuit according to the first detection signal.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Li-Fan Chen, Ching-Ho Li, Ting-You Lin, Chun-Chih Chen, Kai-Chieh Hsu, Chih-Hsuan Lin, Yu-Kai Wang
  • Patent number: 10867989
    Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 15, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hsuan Lin, Shao-Chang Huang, Chun-Chih Chen, Hwa-Chyi Chiou
  • Patent number: 10818653
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 27, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Shang-Chuan Pai, Wei-Chung Wu, Szu-Chi Chen, Sheng-Chih Chuang, Yin-Ting Lin, Pei-Chun Yu, Han-Pei Liu, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Patent number: 10784252
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
  • Patent number: 10719097
    Abstract: A voltage regulation circuit is suitable to provide an output voltage to a core circuit. The voltage regulation circuit includes a pad, a pull-low unit, a first controlling unit, a second controlling unit and a voltage regulation circuit. The pad receives and provides an input voltage. The pull-low unit generates a pull-low voltage according to the input voltage. The first controlling unit generates a first controlling signal according to the input voltage and the pull-low voltage. The second controlling unit generates a second controlling signal according to the input voltage and the first controlling signal. The voltage regulation unit regulates the input voltage according to the first controlling signal and the second controlling signal, so as to generate the output voltage.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Wen-Tsung Wang, Chieh-Yao Chuang, Chi-Hung Lo
  • Publication number: 20200144246
    Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 7, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Jia-Rong YEH, Yeh-Ning JOU, Hwa-Chyi CHIOU
  • Patent number: 10643987
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 5, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin
  • Patent number: 10644501
    Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 5, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Shi-Hsiang Lu, Geeng-Lih Lin