Patents by Inventor Shao-Chang Huang

Shao-Chang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818653
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 27, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Shang-Chuan Pai, Wei-Chung Wu, Szu-Chi Chen, Sheng-Chih Chuang, Yin-Ting Lin, Pei-Chun Yu, Han-Pei Liu, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Publication number: 20200328202
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
  • Patent number: 10784252
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
  • Patent number: 10741539
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 10719097
    Abstract: A voltage regulation circuit is suitable to provide an output voltage to a core circuit. The voltage regulation circuit includes a pad, a pull-low unit, a first controlling unit, a second controlling unit and a voltage regulation circuit. The pad receives and provides an input voltage. The pull-low unit generates a pull-low voltage according to the input voltage. The first controlling unit generates a first controlling signal according to the input voltage and the pull-low voltage. The second controlling unit generates a second controlling signal according to the input voltage and the first controlling signal. The voltage regulation unit regulates the input voltage according to the first controlling signal and the second controlling signal, so as to generate the output voltage.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Wen-Tsung Wang, Chieh-Yao Chuang, Chi-Hung Lo
  • Patent number: 10686993
    Abstract: A correction method for an optical mechanism having an optical member and a fixed portion is provided, including: an external apparatus measures the angle between the optical axis of the optical member and a reference surface of the fixed portion; the result of measuring the angle between the optical axis and the reference surface is compiled into data; the data is input into a control module; the control module transmits a signal to a driving module according to the data; and the driving module drives the optical member to rotate or move relative to the fixed portion upon receiving the signal. The optical mechanism does not include a sensor to detect the angle between the optical axis and the reference surface.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 16, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Shun-Chieh Tang, Shu-Shan Chen, Chih-Wei Weng, Shao-Kuang Huang
  • Publication number: 20200144246
    Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 7, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Jia-Rong YEH, Yeh-Ning JOU, Hwa-Chyi CHIOU
  • Patent number: 10644501
    Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 5, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Shi-Hsiang Lu, Geeng-Lih Lin
  • Patent number: 10643987
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 5, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin
  • Publication number: 20200098740
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 26, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Li-Fan CHEN, Chih-Hsuan LIN, Yu-Kai WANG, Hung-Wei CHEN, Ching-Wen WANG, Ting-You LIN, Chun-Chih CHEN
  • Publication number: 20200083704
    Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes an electrostatic discharge detection circuit, a discharge circuit, and a switch. The electrostatic discharge detection circuit detects whether an electrostatic discharge event occurs at the bounding pad to generate a first detection circuit. The discharge circuit receives the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the discharge circuit provides a discharge path between the bounding pad and a ground terminal according to the first detection signal. The switch is coupled between the core circuit and the ground terminal and controlled by the first detection signal. When the electrostatic discharge event occurs at the bounding pad, the switch is turned off according to the first detection signal.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Jia-Rong YEH, Yeh-Ning JOU, Hsien-Feng LIAO, Yi-Han WU, Chih-Cherng LIAO, Chieh-Yao CHUANG, Wei-Shung CHEN, Ching-Wen CHEN, Pang-Chuan CHEN
  • Publication number: 20200036376
    Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Chun-Chih CHEN, Hwa-Chyi CHIOU
  • Patent number: 10523002
    Abstract: An electrostatic discharge (ESD) protection circuit is provided. A detector is coupled between a first input-output pad and a second input-output pad and detects the voltage levels of the first and second input-output pads to generate a detection signal. A inverter generates a control signal according to the detection signal. A control element is coupled between the first input-output pad and a first node. A current release element is coupled between the first node and the second input-output pad. When the detection signal is at a specific level, the control element and the current release element provide a discharge path to release an ESD current from the first input-output pad to the second input-output pad. When the detection signal is not at the specific level, the control element and the current release element do not provide a discharge path.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 31, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Publication number: 20190393208
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN
  • Publication number: 20190181135
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Shang-Chuan PAI, Wei-Chung WU, Szu-Chi CHEN, Sheng-Chih CHUANG, Yin-Ting LIN, Pei-Chun YU, Han-Pei LIU, Jung-Tsun CHUANG, Chieh-Yao CHUANG, Hung-Wei CHEN
  • Publication number: 20190146178
    Abstract: An optical member driving mechanism is provided, including a first module, a second module, a driving module, and an electronic member module. The driving module can drive the second module to move relative to the first module. The electronic member module includes at least one electronic member, at least one lead frame, and a package member. The lead frame is connected to the electronic member and an external circuit outside the optical member driving mechanism. The package member has a single material and covers the electronic member and the lead frame. The lead frame is exposed from the package member, and the electronic member is not exposed therefrom.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 16, 2019
    Inventors: Chao-Chang HU, Shao-Kuang HUANG, Chih-Wei WENG, Sin-Jhong SONG
  • Patent number: 10262706
    Abstract: An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Ching-Wen Chen, Chieh-Yao Chuang, Yu-Yen Lin
  • Patent number: 10224282
    Abstract: A protection device including a substrate, a first doped region, a first well region, a second doped region, a third doped region, a fourth doped region, a second well region, a fifth doped region, and a sixth doped region is provided. The substrate, the first well region, and the third and the fifth doped regions have a first conductivity type. The first doped and the second well regions are disposed in the substrate. The first, second, fourth, and sixth doped regions and the second well region have a second conductivity type. The first well and the second doped regions are disposed in the first doped region. The second doped region is not in contact with the first well region. The third and fourth doped regions are disposed in the first well region. The fifth and sixth doped regions are disposed in the second well region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 5, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Shao-Chang Huang
  • Patent number: 10177135
    Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: January 8, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin
  • Patent number: 10164627
    Abstract: A power-on control circuit controlling a first output switch and a second output switch is provided. A detecting circuit detects a first voltage to generate a detection signal to a first node. A switching circuit receives the first voltage and a second voltage and transmits the first or second voltage to a second node according to the voltage level of the first node. A setting circuit generates a feedback signal to the first node according to a voltage level of the second node. When the first voltage reaches a first pre-determined value and the second voltage has not reached a second pre-determined value, the switching circuit transmits the second voltage to the second node. When the second voltage reaches the second pre-determined value, the switching circuit transmits the first voltage to the second node.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Chieh-Yao Chuang, Hung-Wei Chen