Patents by Inventor Shao-Ming Yu
Shao-Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957070Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.Type: GrantFiled: August 6, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Ying Lee, Bo-Jiun Lin, Shao-Ming Yu, Yu-Chao Lin
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Publication number: 20240105454Abstract: A method for manufacturing a semiconductor device is described. The method includes the following steps. A low-dimensional material (LDM) layer is formed on a semiconductor substrate, wherein the LDM layer includes sublayers stacked upon one another. A plasma treatment is performed to the LDM layer to transform at least one sublayer into an oxide layer, wherein the plasma treatment is performed under a temperature equivalent to or lower than about 80 degrees Celsius. At least one electrode is disposed over the oxide layer.Type: ApplicationFiled: March 2, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Ying Lee, Wei-Sheng Yun, Yi-Tse HUNG, Shao-Ming YU, Meng-Zhan Li
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Publication number: 20240074334Abstract: A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shao-Ming Yu, Yu-Chao Lin, Tung-Ying Lee
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Publication number: 20240049477Abstract: A memory device and a semiconductor die are provided. The memory device includes single-level-cells (SLCs) and multi-level-cells (MLCs). Each of the SLCs and the MLCs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. The first electrode in each of the MLCs is greater in footprint area as compared to the first electrode in each of the SLCs.Type: ApplicationFiled: August 4, 2022Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Ying Lee, Shao-Ming Yu, Win-San Khwa, Yu-Chao Lin, Chien-Hsing Lee
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Publication number: 20240040938Abstract: A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.Type: ApplicationFiled: July 26, 2022Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Jung-Piao Chiu, Shao-Ming Yu, Yuan-Tien Tu, Tung-Ying Lee
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Publication number: 20240021692Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.Type: ApplicationFiled: August 2, 2023Publication date: January 18, 2024Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
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Publication number: 20240023462Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chao LIN, Yuan-Tien TU, Shao-Ming YU, Tung-Ying LEE
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Publication number: 20240008375Abstract: A memory device and a fabrication method thereof are provided. The memory device includes a substrate, a seed layer over the substrate, a superlattice structure in contact with the seed layer and a top electrode over the superlattice structure. The seed layer comprises carbon and silicon. The superlattice structure comprises first metal layers and second metal layers stacked alternately.Type: ApplicationFiled: July 3, 2022Publication date: January 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chao Lin, Tung-Ying Lee, Shao-Ming Yu
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Patent number: 11856876Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.Type: GrantFiled: May 27, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
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Publication number: 20230411215Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.Type: ApplicationFiled: July 28, 2023Publication date: December 21, 2023Inventors: Shao-Ming YU, Tung Ying LEE, Wei-Sheng YUN, Fu-Hsiang YANG
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Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture
Patent number: 11849655Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.Type: GrantFiled: July 23, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang -
Publication number: 20230389452Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
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Publication number: 20230380305Abstract: A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung-Ying LEE, Shao-Ming YU, Yu-Chao LIN
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SEMICONDUCTOR MEMORY DEVICES WITH ELECTRICALLY ISOLATED STACKED BIT LINES AND METHODS OF MANUFACTURE
Publication number: 20230380310Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang -
Patent number: 11817488Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.Type: GrantFiled: June 8, 2021Date of Patent: November 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
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Patent number: 11818967Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.Type: GrantFiled: June 13, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chao Lin, Yuan-Tien Tu, Shao-Ming Yu, Tung-Ying Lee
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Publication number: 20230363298Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
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Patent number: 11805712Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.Type: GrantFiled: March 15, 2022Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
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Patent number: 11793092Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.Type: GrantFiled: June 27, 2022Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
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Patent number: 11776852Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.Type: GrantFiled: June 14, 2021Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Ming Yu, Tung Ying Lee, Wei-Sheng Yun, Fu-Hsiang Yang