Patents by Inventor Shao-Ming Yu

Shao-Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11849655
    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang
  • Publication number: 20230389452
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Publication number: 20230380310
    Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang
  • Publication number: 20230380305
    Abstract: A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying LEE, Shao-Ming YU, Yu-Chao LIN
  • Patent number: 11818967
    Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao Lin, Yuan-Tien Tu, Shao-Ming Yu, Tung-Ying Lee
  • Patent number: 11817488
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • Publication number: 20230363298
    Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Patent number: 11805712
    Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Patent number: 11793092
    Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Patent number: 11776852
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ming Yu, Tung Ying Lee, Wei-Sheng Yun, Fu-Hsiang Yang
  • Publication number: 20230299203
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Inventors: Shao-Ming YU, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20230263081
    Abstract: A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Kerem Akarvardar, Yu Chao LIN, Wei-Sheng Yun, Shao-Ming Yu, Tzu-Chiang Chen, Tung Ying Lee
  • Patent number: 11721761
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: August 8, 2023
    Assignee: Mosaid Technologies Incorporated
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20230238451
    Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Tung-Ying LEE, Chih-Chieh YEH
  • Patent number: 11621344
    Abstract: A device includes a semiconductor fin, a first epitaxy structure and a gate stack. The semiconductor fin protrudes from a substrate. The first epitaxy feature laterally surrounds a first portion of the semiconductor fin. The gate stack laterally surrounds a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a lower surface roughness than the first epitaxy feature.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Tung-Ying Lee, Chih-Chieh Yeh
  • Patent number: 11588106
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
  • Publication number: 20230045290
    Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Bo-Jiun Lin, Shao-Ming Yu, Yu-Chao Lin
  • Publication number: 20220352465
    Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Tung Ying Lee, Shao-Ming Yu, Yu Chao Lin
  • Publication number: 20220352464
    Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Inventors: Tung Ying Lee, Yu Chao Lin, Shao-Ming Yu
  • Patent number: 11489113
    Abstract: A memory cell includes a storage element layer, a bottom electrode, a top electrode and a liner layer. The storage element layer has a first surface and a concaved second surface opposite to the first surface. The bottom electrode is disposed on the first surface and connected to the storage element layer. The top electrode is on the concaved second surface and connected to the storage element layer. The liner layer is surrounding the storage element layer and the top electrode.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin