Patents by Inventor Shao-Ming Yu
Shao-Ming Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9406782Abstract: A method for fabricating a fin-type field-effect transistor (FinFET) device includes forming a first fin structure over a substrate, forming a dielectric layer over the first fin structures, forming a trench with a vertical profile in the dielectric layer, depositing conformably a first semiconductor material layer over sidewalls and bottom of the trench, depositing a second semiconductor material layer over the first semiconductor material layer to filling in the remaining trench, recessing the dielectric layer to laterally expose the first semiconductor material layer and etching the exposed first semiconductor material layer to reveal the second semiconductor material layer.Type: GrantFiled: June 27, 2014Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Yu, Shao-Ming Yu
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Patent number: 9368446Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.Type: GrantFiled: December 29, 2014Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20160163851Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.Type: ApplicationFiled: December 30, 2014Publication date: June 9, 2016Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
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Patent number: 9324866Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.Type: GrantFiled: January 23, 2012Date of Patent: April 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
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Patent number: 9245080Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.Type: GrantFiled: July 22, 2014Date of Patent: January 26, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Ming Yu, Chang-Yun Chang
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Publication number: 20150380525Abstract: A method for fabricating a fin-type field-effect transistor (FinFET) device includes forming a first fin structure over a substrate, forming a dielectric layer over the first fin structures, forming a trench with a vertical profile in the dielectric layer, depositing conformably a first semiconductor material layer over sidewalls and bottom of the trench, depositing a second semiconductor material layer over the first semiconductor material layer to filling in the remaining trench, recessing the dielectric layer to laterally expose the first semiconductor material layer and etching the exposed first semiconductor material layer to reveal the second semiconductor material layer.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Inventors: Chih-Hao Yu, Shao-Ming Yu
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Publication number: 20150115373Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.Type: ApplicationFiled: December 30, 2014Publication date: April 30, 2015Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
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Publication number: 20150108651Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.Type: ApplicationFiled: December 29, 2014Publication date: April 23, 2015Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 8921136Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.Type: GrantFiled: January 17, 2013Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20140331192Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.Type: ApplicationFiled: July 22, 2014Publication date: November 6, 2014Inventors: Shao-Ming YU, Chang-Yun CHANG
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Patent number: 8881084Abstract: A method for generating a layout for a semiconductor device is disclosed. The method includes: receiving a first layout. A portion of the first layout is defined as a first FinFET region. The first FinFET region has first and second sides that each extend approximately in a first direction. The method includes performing a first design rule check (DRC) simulation. The method includes obtaining a first DRC simulation result. The method includes defining a second FinFET region by moving the first side in a second direction perpendicular to the first direction. The method includes performing a second DRC simulation. The method includes obtaining a second DRC simulation result. The method includes selecting one of the first and second FinFET regions based on the first and second DRC simulation results. The method includes generating a second layout using the selected FinFET region.Type: GrantFiled: May 14, 2010Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
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Patent number: 8813014Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.Type: GrantFiled: December 30, 2009Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Ming Yu, Chang-Yun Chang
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Patent number: 8809202Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.Type: GrantFiled: February 14, 2012Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hui Weng, Wei-Sheng Yun, Shao-Ming Yu, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
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Publication number: 20140197499Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.Type: ApplicationFiled: January 17, 2013Publication date: July 17, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 8747992Abstract: In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.Type: GrantFiled: June 13, 2013Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Shao-Ming Yu
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Patent number: 8709928Abstract: An angled implantation process is used in implanting semiconductor fins of a semiconductor device and provides for covering some but not necessarily all of semiconductor fins of a first type with patterned photoresist, and implanting using an implant angle such that all semiconductor fins of a second type are implanted and none of the semiconductor fins of the first type, are implanted. A higher tilt or implant angle is achieved due to the reduced portions of patterned photoresist, that are used.Type: GrantFiled: January 19, 2010Date of Patent: April 29, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Ming Yu, Chang-Yun Chang
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Patent number: 8637135Abstract: In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.Type: GrantFiled: August 13, 2010Date of Patent: January 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Shao-Ming Yu
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Patent number: 8623718Abstract: In a method for forming FinFETs, a photo resist is formed to cover a first semiconductor fin in a wafer, wherein a second semiconductor fin adjacent to the first semiconductor fin is not covered by the photo resist. An edge of the photo resist between and parallel to the first and the second semiconductor fins is closer to the first semiconductor fin than to the second semiconductor fin. A tilt implantation is performed to form a lightly-doped source/drain region in the second semiconductor fin, wherein the first tilt implantation is tilted from the second semiconductor fin toward the first semiconductor fin.Type: GrantFiled: September 28, 2011Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Yuan, Tsung-Lin Lee, Shao-Ming Yu, Clement Hsingjen Wann
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Patent number: 8621398Abstract: A method for generating a layout for a FinFET device is disclosed. The method includes receiving an initial layout containing an active region that has an edge extending in a first direction. The method includes designating a portion of the layout as a first region. The first region contains the active region. The method includes designating an elongate portion of the first region as a second region that extends in the first direction. The method includes designating a different elongate portion of the first region as a third region that extends in the first direction and that is adjacent to the second region in a second direction perpendicular to the first direction. The method includes enlarging the active region if the edge of the active region falls inside the third region, and shrinking the active region if the edge of the active region falls outside the third region.Type: GrantFiled: May 14, 2010Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Jung Shen, Shao-Ming Yu, Chih-Sheng Chang
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Publication number: 20130270653Abstract: In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.Type: ApplicationFiled: June 13, 2013Publication date: October 17, 2013Inventors: Tsung-Lin Lee, Shao-Ming Yu