Abstract: Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.

Abstract: A first embodiment of the present invention is a system for generating a voltage comprising a comparator operable to compare an operation voltage to a reference voltage, control logic operable to selectively output as a control signal an incremented signal or a decremented signal based on a comparison of the operation voltage to the reference voltage by the comparator, and a device module operable to increase or decrease the operation voltage based on the control signal.

Abstract: A method of forming an integrated circuit structure includes providing a chip; forming a static random access memory (SRAM) cell including a transistor on the chip; and forming a bias transistor configured to gate a power supply voltage provided to the SRAM cell on the chip. The bias transistor and the transistor of the SRAM cell are formed simultaneously.

Abstract: Some embodiments regard a method comprising: during a leakage sampling phase, recognizing a voltage level dropped due to a leakage current associated with a signal linestoring the voltage level; and during a reading phase, using the voltage level to provide an amount of compensation current to the signal line.

Abstract: This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.

Abstract: A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.

Abstract: This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.

Abstract: Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.

Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.

Abstract: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a non-linear way; a charging capacitor having a first end coupled to the load circuit; a charging path between a second end of the charging capacitor and the first end of the bias circuit, wherein the charging path is responsive to a clock signal; a discharging path between the second end of the charging capacitor and the low voltage reference potential, wherein the discharging path is responsive to the clock signal; and a switch circuit connected to the first end of the charging capacitor for setting a voltage thereon, wherein the switch circuit is responsive to the clock signal.

Abstract: In a standard Flash EPROM, a plurality of flash memory cells are arranged in an array of rows and columns. In order to determine the programming state of each cell, the magnitude of the cell read current is measured using a reference current source set to approximately 25 uA. The memory cell being examined is connected with the drain wired to a positive voltage between about 1 to 2 volts. The source of the memory cell is connected to the current source. The control gate voltage is set to approximately 5V. An unprogrammed memory cell will have a drain current equal to that of the reference current source and the cell output will be slightly less than the drain voltage (logic 1). Under these conditions, a programmed memory cell, having a higher threshold voltage, will conduct only leakage currents. This results in the cell output being very close to ground potential (logic 0). Older technologies utilized fixed current sources for the reference current.

Abstract: A method and circuit for improving reliability in charge pumping circuits. The reliability of charge pump circuits is degraded by continual voltage stress across the gate oxides of the field effect transistors in the charge pumping circuit. In this method and circuit diodes, or diode connected transistors, are connected to the gates of the field effect transistors in the charge pump circuits. The anodes of the diodes are connected to the gates of the FETs and the cathodes of the diodes are connected to the output node of the charge pump circuit. When the voltage at the output node of the charge pump circuit is high the diodes have no effect. When current is delivered to the load connected to the output node the voltage at the output node drops and the diodes help discharge the internal nodes of the charge pump circuits thereby reducing the voltage across the FET gate oxides.

Abstract: A method and circuit for improving reliability in charge pumping circuits. The reliability of charge pump circuits is degraded by continual voltage stress across the gate oxides of the field effect transistors in the charge pumping circuit. In this method and circuit, either diodes, or diode connected transistors, are connected to the gates of the field effect transistors in the charge pump circuits. The anodes of the diodes are connected to the gates of the FETs and the cathodes of the diodes are connected to the output node of the charge pump circuit. When the voltage at the output node of the charge pump circuit is high the diodes have no effect. When current is delivered to the load connected to the output node the voltage at the output node drops and the diodes help discharge the internal nodes of the charge pump circuits thereby reducing the voltage across the FET gate oxides.

Abstract: A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming simulations on the prototype, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line by skipping certain Flash/EEPROM steps and then implanting the ROM code into the final ROM product. The method improves turn-around-time in the manufacturing line, and reduces cost to the customer. A method of doing business is also disclosed directed to providing ROM products to a customer without much redesign time and effort on the part of the customer.

Abstract: In a standard Flash EPROM, a plurality of flash memory cells are arranged in an array of rows and columns. In order to determine the programming state of each cell, the magnitude of the cell read current is measured using a reference current source set to approximately 25uA. The memory cell being examined is connected with the drain wired to a positive voltage between about 1 to 2 volts. The source of the memory cell is connected to the current source. The control gate voltage is set to approximately 5V. An unprogrammed memory cell will have a drain current equal to that of the reference current source and the cell output will be slightly less than the drain voltage (logic 1). Under these conditions, a programmed memory cell, having a higher threshold voltage, will conduct only leakage currents. This results in the cell output being very close to ground potential (logic 0). Older technologies utilized fixed current sources for the reference current.

Abstract: In a standard Flash EPROM, a plurality of flash memory cells are arranged in an array of rows and columns. In order to determine the programming state of each cell, the magnitude of the cell read current is measured using a reference current source set to approximately 25 uA. The memory cell being examined is connected with the drain wired to a positive voltage between about 1 to 2 volts. The source of the memory cell is connected to the current source. The control gate voltage is set to approximately 5V. An unprogrammed memory cell will have a drain current equal to that of the reference current source and the cell output will be slightly less than the drain voltage (logic 1). Under these conditions, a programmed memory cell, having a higher threshold voltage, will conduct only leakage currents. This results in the cell output being very close to ground potential (logic 0). Older technologies utilized fixed current sources for the reference current.

Abstract: An output stage and method for a charge pump circuit which substantially reduces the degradation of the output voltage. A first NMOS transistor has its source connected to an input node and its drain connected to a second node. A second NMOS transistor has its source connected to the input node, its gate connected to the drain of the first NMOS transistor, and its drain connected to the gate of the first NMOS transistor. A capacitor is connected between a second clock signal and the drain of the second NMOS transistor. Another capacitor is connected between a first clock signal and an intermediate node. The key part of the invention is a diode pair connected anode of one to the cathode of the other and inserted between the intermediate node and the drain of the first NMOS transistor.