Abstract: An embodiment includes a computer program product for providing a yield prediction. The computer program product has a non-transitory computer readable medium with a computer program embodied thereon. The computer program comprises computer program code for obtaining a representation of a circuit. The circuit comprises a common path and a critical path, and the critical path represents multiple parallel paths. The computer program further comprises computer program code for obtaining a first table representing the common path and a second table representing the multiple parallel paths and computer program code for performing a variable based simulation based on the representation of the circuit, the first table, and the second table. The computer program also comprises computer program code for determining a result indication of each of the multiple parallel paths based on the variable based simulation compared with a predetermined specification.

Abstract: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.

Abstract: A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.

Abstract: Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Abstract: A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit.

Abstract: A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.

Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.

Abstract: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, the first blocking device being configured to conduct active current when the first signal is in static state or transitions from a logic HIGH to a logic LOW, and the first blocking device being configured to shut off active current when the first signal transitions from the logic LOW to the logic HIGH.

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract: A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit.

Abstract: A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node.

Abstract: A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved.

Abstract: In an embodiment related to a sense amplifier, the sense amplifier includes a pair of transistors (e.g., transistors P2 and P3) that, when appropriate, enables data on input lines DL and DLB to be preset directly to the internal nodes (e.g., nodes S and SB) of the sense amplifier, from which the data can be read out. In addition, this pair of transistors P2 and P3 also allows the internal nodes S and SB to share the pre-charge mechanisms of lines DL and DLB.

Abstract: Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.

Abstract: A first embodiment of the present invention is a system for generating a voltage comprising a comparator operable to compare an operation voltage to a reference voltage, control logic operable to selectively output as a control signal an incremented signal or a decremented signal based on a comparison of the operation voltage to the reference voltage by the comparator, and a device module operable to increase or decrease the operation voltage based on the control signal.

Abstract: A method of forming an integrated circuit structure includes providing a chip; forming a static random access memory (SRAM) cell including a transistor on the chip; and forming a bias transistor configured to gate a power supply voltage provided to the SRAM cell on the chip. The bias transistor and the transistor of the SRAM cell are formed simultaneously.

Abstract: Some embodiments regard a method comprising: during a leakage sampling phase, recognizing a voltage level dropped due to a leakage current associated with a signal linestoring the voltage level; and during a reading phase, using the voltage level to provide an amount of compensation current to the signal line.