Abstract: Systems and methods for controlling a sense amplifier are provided. First and second MOS transistors of a first type are connected in series between a first voltage potential and a node. A gate terminal of the first MOS transistor is coupled to a first data. A gate terminal of the second MOS transistor is coupled to a second data line. A third MOS transistor of a second type is connected between the node and a second voltage potential. The third MOS transistor has a gate terminal coupled to the first data line. A fourth MOS transistor of the second type is connected between the node and the second voltage potential in a parallel arrangement with the third MOS transistor. The fourth MOS transistor has a gate terminal coupled to the second data line. A control signal provided to a sense amplifier is based on a voltage of the node.

Abstract: A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.

Abstract: The present disclosure relates to a semiconductor structure which includes a first row of diffusion strap having two sections separated by a first distance, a second row of diffusion strap having two sections separated by the first distance, a third row of diffusion strap having two sections separated by the first distance, a fourth row of diffusion strap having two sections separated by the first distance, a first row of conductive strap over the first row of diffusion strap and the second row of diffusion strap, and a second row of conductive strap over the third row of diffusion strap and the fourth row of diffusion strap. The first row of conductive strap has two sections separated by a second distance. The second row of conductive strap has having two sections separated by the second distance, wherein the second distance is greater than the first distance.

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Abstract: A fuse structure comprises a first conductive layer on a first level. The first conductive layer comprises a fuse line extending in a first direction. The fuse line has a first end portion, a second end portion opposite the first end portion, and a fuse link portion connecting the first end portion and the second end portion. The first conductive layer also comprises lines parallel to the fuse line, the lines being aligned in the first direction and being separated from one another by a first distance measured in the first direction. The fuse structure also comprises a second conductive layer on a second level different from the first level and coupled with the first conductive layer. The second conductive layer has parallel lines extending in a second direction, the parallel lines being separated by a second distance measured in a third direction orthogonal to the second direction.

Abstract: A fuse structure comprises a first conductive layer on a first level. The first conductive layer comprises a fuse line extending in a first direction. The fuse line has a first end portion, a second end portion opposite the first end portion, and a fuse link portion connecting the first end portion and the second end portion. The first conductive layer also comprises lines parallel to the fuse line, the lines being aligned in the first direction and being separated from one another by a first distance measured in the first direction. The fuse structure also comprises a second conductive layer on a second level different from the first level and coupled with the first conductive layer. The second conductive layer has parallel lines extending in a second direction, the parallel lines being separated by a second distance measured in a third direction orthogonal to the second direction.

Abstract: An embodiment includes a computer program product for providing a yield prediction. The computer program product has a non-transitory computer readable medium with a computer program embodied thereon. The computer program comprises computer program code for obtaining a representation of a circuit. The circuit comprises a common path and a critical path, and the critical path represents multiple parallel paths. The computer program further comprises computer program code for obtaining a first table representing the common path and a second table representing the multiple parallel paths and computer program code for performing a variable based simulation based on the representation of the circuit, the first table, and the second table. The computer program also comprises computer program code for determining a result indication of each of the multiple parallel paths based on the variable based simulation compared with a predetermined specification.

Abstract: A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point.

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.

Abstract: Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed.

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: Methods and apparatus for the encoding of an input sequence of digit data into a sequence of storage cells of a ROM device are disclosed. The input sequence is divided into a first kind of groups and a second kind of groups. A first kind of group comprises a plurality of consecutive first digits, two first kind of groups are separated by a second kind of group, the second kind of group comprises consecutive digits without any consecutive first digits, and the second kind of group has a starting digit which is the second digit. A starting storage cell is programmed to the active state to store the starting digit of the second kind of group. The rest digits of the second kind of group are programmed one digit at a time, based on a shared terminal which has been programmed for the proceeding storage cell.

Abstract: A circuit includes one or more memory cells, a data line associated with the one or more memory cells, one or more reference cells, a reference data line associated with the one or more reference cells, a first circuit coupled to the reference data line and the data line, and a second circuit. The first circuit is configured to output a first logical value based on a voltage level of the data line upon occurrence of a voltage level of the reference data line reaching a trip point. The second circuit is configured to output a second logical value based on the voltage level on the data line prior to the occurrence of the voltage level of the reference data line reaching the trip point, and to output the first logical value after the occurrence of the voltage level of the reference data line reaching the trip point.

Abstract: Methods and apparatus for the encoding of an input sequence of digit data into a sequence of storage cells of a ROM device are disclosed. The input sequence is divided into a first kind of groups and a second kind of groups. A first kind of group comprises a plurality of consecutive first digits, two first kind of groups are separated by a second kind of group, the second kind of group comprises consecutive digits without any consecutive first digits, and the second kind of group has a starting digit which is the second digit. A starting storage cell is programmed to the active state to store the starting digit of the second kind of group. The rest digits of the second kind of group are programmed one digit at a time, based on a shared terminal which has been programmed for the proceeding storage cell.

Abstract: An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.

Abstract: A circuit includes a memory array comprising K number of rows. The circuit further including a reference column. The reference column includes M cells of a first cell type configured to provide a first leakage current, K-M cells of a second cell type different from the first cell type, the K-M cells are configured to provide a second leakage current, and a reference data line connected to the cells of the first cell type and the cells of the second cell type. The circuit further includes a sensing circuit configured to determine a value stored in a memory cell of the memory array based on a voltage of the reference data line.

Abstract: A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.