Patents by Inventor Shaowu HUANG
Shaowu HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967575Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.Type: GrantFiled: February 25, 2022Date of Patent: April 23, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Guilian Gao, Javier A. DeLaCruz, Shaowu Huang, Liang Wang, Gaius Gillman Fountain, Jr., Rajesh Katkar, Cyprian Emeka Uzoh
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Publication number: 20240118492Abstract: Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers.Type: ApplicationFiled: November 14, 2023Publication date: April 11, 2024Inventors: Shaowu HUANG, Javier A. DELACRUZ, Liang WANG, Guilian GAO
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Patent number: 11903123Abstract: An interface in a communications system includes a physical layer transceiver (PHY) for coupling to a wireline channel medium, and for coupling to a functional device via a single-ended cable. The PHY is an integrated circuit (IC) device having first and second differential input/output (I/O) conductors for coupling to the functional device, an impedance element configured to terminate a first one of the differential I/O conductors to a system ground, a second one of the differential I/O conductors being coupled to the single-ended cable, and a common-mode filter coupled to both of the differential I/O conductors. The PHY may further include a printed circuit board (PCB), with the IC device being mounted on the PCB, the first and second differential I/O conductors being signal traces on the PCB. The single-ended cable may be a coaxial cable.Type: GrantFiled: March 10, 2022Date of Patent: February 13, 2024Assignee: Marvell Asia Pte LtdInventors: Shaowu Huang, Dance Wu
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Patent number: 11860415Abstract: Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers.Type: GrantFiled: October 21, 2021Date of Patent: January 2, 2024Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Shaowu Huang, Javier A. Delacruz, Liang Wang, Guilian Gao
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Publication number: 20230420313Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.Type: ApplicationFiled: September 7, 2023Publication date: December 28, 2023Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed
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Patent number: 11837556Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.Type: GrantFiled: April 14, 2022Date of Patent: December 5, 2023Assignee: Adeia Semiconductor Technologies LLCInventors: Shaowu Huang, Javier A. Delacruz
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Patent number: 11823906Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.Type: GrantFiled: February 18, 2022Date of Patent: November 21, 2023Assignee: Xcelsis CorporationInventors: Javier A. DeLaCruz, Steven L. Teig, Shaowu Huang, William C. Plants, David Edward Fisch
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Publication number: 20230317591Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.Type: ApplicationFiled: December 29, 2022Publication date: October 5, 2023Inventors: Belgacem Haba, llyas Mohammed, Rajesh Katkar, Gabriel Z. Guevara, Javier A. DeLaCruz, Shaowu Huang, Laura Willis Mirkarimi
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Patent number: 11765822Abstract: Electronic apparatus includes a dielectric substrate and alternating layers of conducting and dielectric materials disposed over the dielectric substrate, including at least first and second patterned layers of the conducting material separated by an intervening layer of the dielectric material. A conductive trace is disposed within the first patterned layer of the conducting material. A conductive mesh extends within the second patterned layer of the conducting material over a region that overlaps transversely with at least a part of the conductive trace in the first patterned layer.Type: GrantFiled: September 1, 2021Date of Patent: September 19, 2023Assignee: MARVELL ASIA PTE LTDInventors: Shaowu Huang, Dance Wu
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Patent number: 11737207Abstract: A printed circuit board (PCB) includes a substrate defining a major plane. A first side of the major plane is configured for mounting of functional circuit elements. A cable connector is mounted on a second side of the major plane of the substrate, opposite the first side, for coupling to a shielded radiofrequency (RF) communications cable. At least one component grounding layer is parallel to the major plane and configured for coupling to the functional elements. At least one cable grounding layer is parallel to the major plane and is separated from the at least one component grounding layer. Each cable grounding layer in the at least one cable grounding layer is coextensive with the substrate and is configured for coupling, through the connector, to shielding of the shielded RF communications cable, without coupling to any other component. Nodes of an RF communications system may be mounted on such PCBs.Type: GrantFiled: March 5, 2021Date of Patent: August 22, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Shaowu Huang, Dance Wu
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Publication number: 20230260858Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.Type: ApplicationFiled: December 28, 2022Publication date: August 17, 2023Inventors: Shaowu Huang, Javier A. DeLaCruz, Liang Wang, Rajesh Katkar, Belgacem Haba
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Patent number: 11711225Abstract: An apparatus for filtering an electrical power signal in an Ethernet communication system includes a link interface, a power interface, and a filter connected between the link interface and the power interface. The link interface is configured to connect to an Ethernet link. The power interface is configured to connect to one or both of (i) a power-supply that supplies the electrical power signal for transfer over the Ethernet link, and (ii) a circuit that consumes the electrical power signal transferred over the Ethernet link. The filter includes at least (i) a primary inductor configured to filter the electrical power signal transferred to or from the Ethernet link, and (ii) one or more complementary inductors connected in series with the primary inductor, the one or more complementary inductors configured to reduce a parasitic capacitance of the filter.Type: GrantFiled: October 10, 2021Date of Patent: July 25, 2023Assignee: MARVELL ASIA PTE LTDInventors: Shaowu Huang, Dance Wu
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Patent number: 11711591Abstract: A radiofrequency (RF) wireline communications system includes an interference filter for filtering interference noise at a cable interface that couples a cable of the system to functional circuitry. The interference filter includes a first termination resistance element coupled between a first cable conductor and a system ground, and a first termination reactance element coupled to the first termination resistance element.Type: GrantFiled: April 27, 2021Date of Patent: July 25, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Shaowu Huang, Dance Wu
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Patent number: 11696426Abstract: A network communication device includes communication circuitry configured to communicate signals over a network cable, and a connector configured to connect to the network cable. The connector includes one or more signal terminals, an inner shield connection and an outer shield connection. The one or more signal terminals are configured to connect to one or more signal conductors of the network cable for communicating the signals. The inner shield connection surrounds the one or more signal terminals and is connected to a circuit ground of the communication circuitry. The outer shield connection surrounds the inner shield connection and is connected to an additional ground of the network communication device, the additional ground being different from the circuit ground.Type: GrantFiled: February 24, 2021Date of Patent: July 4, 2023Assignee: MARVELL ASIA PTE LTDInventors: Shaowu Huang, Dance Wu
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Publication number: 20230187398Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.Type: ApplicationFiled: December 28, 2022Publication date: June 15, 2023Inventors: Guilian GAO, Javier A. DELACRUZ, Shaowu HUANG, Liang WANG, Gaius Giliman FOUNTAIN, JR., Rajesh KATKAR, Cyprian Emeka UZOH
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Patent number: 11626363Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.Type: GrantFiled: December 28, 2017Date of Patent: April 11, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar, Gabriel Z. Guevara, Javier A. DeLaCruz, Shaowu Huang, Laura Wills Mirkarimi
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Publication number: 20230089254Abstract: A printed circuit board (PCB) and a method of manufacturing the same is described. The PCB includes a substrate defining a major plane and an integrated electromagnetic interference and compatibility (EMC/EMI) shielding enclosure configured to enclose the substrate. The shielding enclosure includes a metallic top layer deposited on top of the major plane of the substrate so as to envelope an uppermost layer of the substrate, a metallic bottom layer deposited on bottom of the major plane of the substrate so as to envelope a bottommost layer of the substrate, and a metallic side layer formed along a length of one or more edges of the substrate to electrically connect the metallic top layer and the metallic bottom layer.Type: ApplicationFiled: December 1, 2022Publication date: March 23, 2023Inventors: Shaowu Huang, Dance Wu
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Patent number: 11600542Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.Type: GrantFiled: January 11, 2021Date of Patent: March 7, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Shaowu Huang, Javier A. DeLaCruz, Liang Wang, Rajesh Katkar, Belgacem Haba
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Patent number: 11570887Abstract: A printed circuit board (PCB) and a method of manufacturing the same is described. The PCB includes a substrate defining a major plane and an integrated electromagnetic interference and compatibility (EMC/EMI) shielding enclosure configured to enclose the substrate. The shielding enclosure includes a metallic top layer deposited on top of the major plane of the substrate so as to envelop an uppermost layer of the substrate, a metallic bottom layer deposited on bottom of the major plane of the substrate so as to envelop a bottommost layer of the substrate, and a metallic side layer formed along a length of one or more edges of the substrate to electrically connect the metallic top layer and the metallic bottom layer.Type: GrantFiled: March 18, 2021Date of Patent: January 31, 2023Assignee: Marvell Asia Pte, Ltd.Inventors: Shaowu Huang, Dance Wu
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Publication number: 20220415734Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.Type: ApplicationFiled: June 9, 2022Publication date: December 29, 2022Inventors: Rajesh Katkar, Liang Wang, Cyprian Emeka Uzoh, Shaowu Huang, Guilian Gao, Ilyas Mohammed