Patents by Inventor Sharad Kumar

Sharad Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250252443
    Abstract: Various embodiments for remotely sharing a payment instrument of a first user to a client device of a second user are provided. In some embodiments, a system is configured to receive display an authentication user interface for the second user based at least in part on a selection of an authentication hyperlink. The authentication user interface can be associated with accessing a virtual payment instrument that is linked to a transaction account of the first user. The system can be configured to transmit a user credential for the second user using the authentication user interface. The virtual payment instrument can be received based at least in part on an authentication of the user credential for the second user. A wallet user interface can be displayed that includes the virtual payment instrument based at least in part on a receipt of the virtual payment instrument.
    Type: Application
    Filed: March 28, 2025
    Publication date: August 7, 2025
    Inventors: Pankaj Mehla, Anuj Goyal, Anthony Jaleel Wooten, Yogesh Edekar, Moses Godinez, Sridevi Majeti, Sharad Kumar, Nicholas Martinez
  • Publication number: 20250218506
    Abstract: A static random-access memory is provided with a double-pumped operation in which a read operation to a multiplexed group of columns of bitcells may occur in a first portion of a memory clock cycle and in which a write operation to a write-selected column in the multiplexed group of columns of bitcells may occur in a second portion of the memory clock cycle. The write operation to the write-selected column occurs without any precharging of bit lines in the write-selected column during read and write operations.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 3, 2025
    Inventors: Pradeep RAJ, Akshdeepika LNU, Abhishek DALAL, Rahul SAHU, Sharad Kumar GUPTA, Sherin BOSE, Sakshi SINGHAL
  • Patent number: 12327599
    Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.
    Type: Grant
    Filed: March 14, 2024
    Date of Patent: June 10, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Sahu, Sharad Kumar Gupta, Jung Pill Kim, Chulmin Jung, Jais Abraham
  • Publication number: 20250184023
    Abstract: Aspects of the subject disclosure may include, for example, a device, including: a processing system including a processor; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: receiving an indication of a priority level of an interworking function used by a boundary clock node; and selecting a best master clock using an algorithm that considers the priority level of the boundary clock node. Other embodiments are disclosed.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 5, 2025
    Applicant: CIENA CORPORATION
    Inventors: Sharad Kumar Srivastava, Vineet Kumar Garg, Krishan Singh, Vikas Joshi
  • Publication number: 20250184025
    Abstract: Aspects of the subject disclosure may include, for example, a device, including: a processing system including a processor; a clock; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: advertising via Border Gateway Protocol (BGP) a capability as a precision timing protocol (PTP) master clock through an Internet Protocol (IP)/Multi-Protocol Label Switching (MPLS) network, wherein the advertising includes an IP address of the device; receiving a unicast signaling mechanism from a PTP client node in the network; and sending clock messages to the PTP client node responsive to accepting the PTP client node. Other embodiments are disclosed.
    Type: Application
    Filed: January 30, 2025
    Publication date: June 5, 2025
    Applicant: CIENA CORPORATION
    Inventors: Sharad Kumar Srivastava, Vineet Kumar Garg, Krishan Singh, Vijendra Singh Chauhan
  • Publication number: 20250184024
    Abstract: Aspects of the subject disclosure may include, for example, a device that includes a processing system including a processor; a clock; and a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations of: advertising a capability as a precision timing protocol (PTP) master clock through an Internet Protocol (IP) network, wherein the advertising includes an IP address of the device; receiving a unicast signaling mechanism from a PTP client node in the network; and sending clock messages to the PTP client node responsive to accepting the PTP client node. Other embodiments are disclosed.
    Type: Application
    Filed: January 23, 2024
    Publication date: June 5, 2025
    Applicant: CIENA CORPORATION
    Inventors: Sharad Kumar Srivastava, Vineet Kumar Garg, Krishan Singh, Vijendra Singh Chauhan
  • Publication number: 20250072110
    Abstract: A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Kamesh MEDISETTI, Sharad Kumar GUPTA, Sudesh Chandra SRIVASTAVA, Somesh AGARWAL, Udayakiran Kumar YALLAMARAJU, Anand Ashok BALIGATTI, Girish T P, Ankur MEHROTRA, Gousulu KANDUKURU, Abhinav CHAUHAN, Amit KASHYAP, Parissa NAJDESAMII
  • Patent number: 12183393
    Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.
    Type: Grant
    Filed: March 12, 2024
    Date of Patent: December 31, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta
  • Publication number: 20240312496
    Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Inventors: Pradeep RAJ, Rahul SAHU, Sharad Kumar GUPTA, Hemant PATEL, Diwakar SINGH
  • Publication number: 20240270752
    Abstract: The present invention relates to compounds of formula (I) or (II) pharmaceutically acceptable salts, solvates, tautomers, stereoisomers thereof, including enantiomers, diastereomers, racemic mixtures, mixtures of enantiomers, or combinations thereof, and pharmaceutical uses of the compounds.
    Type: Application
    Filed: September 8, 2023
    Publication date: August 15, 2024
    Inventors: András MÁLNÁSI-CSIZMADIA, Máté GYIMESI, András SZABÓ, Péter HÁRI, Suthar Sharad KUMAR, Mihály KOVÁCS, Ádám István HORVÁTH, Máté PÉNZES, István LORINCZ, László VÉGNER, Zoltán SIMON, Sándor BÁTORI, Zoltán SZÖNYEGI, Vajk HORVÁTH, József RÉPÁSI
  • Patent number: 12047073
    Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: July 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta, Chulmin Jung
  • Publication number: 20240221828
    Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.
    Type: Application
    Filed: March 12, 2024
    Publication date: July 4, 2024
    Inventors: Pradeep RAJ, Rahul SAHU, Sharad Kumar GUPTA
  • Publication number: 20240221853
    Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Inventors: Rahul SAHU, Sharad Kumar GUPTA, Jung Pill KIM, Chulmin JUNG, Jais ABRAHAM
  • Patent number: 12020766
    Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: June 25, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta, Hemant Patel, Diwakar Singh
  • Patent number: 11972834
    Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 30, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Adithya Bhaskaran, Rahul Sahu, Sharad Kumar Gupta
  • Patent number: 11955169
    Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: April 9, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta
  • Patent number: 11935606
    Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Sahu, Sharad Kumar Gupta, Jung Pill Kim, Chulmin Jung, Jais Abraham
  • Patent number: 11845758
    Abstract: The present invention relates to compounds of formula (I) or (II) pharmaceutically acceptable salts, solvates, tautomers, stereoisomers thereof, including enantiomers, diastereomers, racemic mixtures, mixtures of enantiomers, or combinations thereof, and pharmaceutical uses of the compounds.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: December 19, 2023
    Assignees: PRINTNET KERESKEDELMI ÉS SZOLGÁLTATÓ KFT., EÖTVÖS LORÁND TUDOMÁNYEGYETEM
    Inventors: András Málnási-Csizmadia, Máté Gyimesi, András Szabó, Péter Hári, Suthar Sharad Kumar, Mihály Kovács, Ádám István Horváth, Máté Pénzes, István Lörincz, László Végner, Zoltán Simon, Sándor Bátori, Zoltán Szönyegi, Vajik Horváth, József Répási
  • Patent number: 11837313
    Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta, Chulmin Jung
  • Publication number: 20230385801
    Abstract: A consumer may initiate a transaction using a transaction account. The transaction account issuer may transmit a notification to the consumer that the transaction has been authorized. The consumer may select requestees with whom to split the transaction. The transaction account issuer may transmit notifications to requestees to request payment from the requestees. The transaction account issuer may transfer the payment from a transaction account of the requestee to the consumer's transaction account.
    Type: Application
    Filed: June 7, 2023
    Publication date: November 30, 2023
    Inventors: Sharad Kumar, John Roam, Amit Sahu, Mahi Sethuraman, Sriram Sundararajan