Abstract: A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

Abstract: The present invention relates to compounds of formula (I) or (II) pharmaceutically acceptable salts, solvates, tautomers, stereoisomers thereof, including enantiomers, diastereomers, racemic mixtures, mixtures of enantiomers, or combinations thereof, and pharmaceutical uses of the compounds.

Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

Abstract: The present invention relates to compounds of formula (I) or (II) pharmaceutically acceptable salts, solvates, tautomers, stereoisomers thereof, including enantiomers, diastereomers, racemic mixtures, mixtures of enantiomers, or combinations thereof, and pharmaceutical uses of the compounds.

Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

Abstract: A consumer may initiate a transaction using a transaction account. The transaction account issuer may transmit a notification to the consumer that the transaction has been authorized. The consumer may select requestees with whom to split the transaction. The transaction account issuer may transmit notifications to requestees to request payment from the requestees. The transaction account issuer may transfer the payment from a transaction account of the requestee to the consumer's transaction account.

Abstract: The present invention relates to compounds of formula (I) or (II) pharmaceutically acceptable salts, solvates, tautomers, stereoisomers thereof, including enantiomers, diastereomers, racemic mixtures, mixtures of enantiomers, or combinations thereof, and pharmaceutical uses of the compounds.

Abstract: With an offer server computer system: receiving a first digital image file, a first mapping of product codes to audience segment identifiers, and a temporary price reduction (TPR) offer dataset; mapping a target identifier for an end user device of a consumer to an audience segment identifier; in response to determining, based on the audience segment identifier, that the TPR offer dataset has a product code and a retailer identifier that map to the audience segment identifier, and an effective date value that includes a current date value, and the retailer identifier corresponds to a retailer location within a specified distance of a then-current location of the end user computing device: creating and storing a digital offer dataset comprising both the first digital image file and a second digital image file that presents data elements of the TPR offer dataset; causing transmission of the dataset to the end user device.

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

Abstract: The present invention relates to compounds of formula (I) or (II) pharmaceutically acceptable salts, solvates, tautomers, stereoisomers thereof, including enantiomers, diastereomers, racemic mixtures, mixtures of enantiomers, or combinations thereof, and pharmaceutical uses of the compounds.

Abstract: At least some embodiments are directed to an exemplary computer-based electronic activity tracking system that detects activity patterns receiving data values that represent at least one electronic activity. The exemplary electronic activity tracking system includes a detector of unsecure electronic activities that identifies electronic activity patterns performed by a user or non-person entity. The detector of unsecure electronic activities utilizes unsupervised machine learning techniques to detect the electronic activity patterns. The detected electronic activity patterns correspond to unsecure or malicious electronic activities. The electronic activity tracking system outputs notifications indicative of identified unsecure or malicious activity patterns and identifies entities associated with such unsecure or malicious activity patterns. The exemplary electronic activity tracking system implements a graphical user interface operated from a client computing device.

Abstract: A consumer may initiate a transaction using a transaction account. The transaction account issuer may transmit a notification to the consumer that the transaction has been authorized. The consumer may select requestees with whom to split the transaction. The transaction account issuer may transmit notifications to requestees to request payment from the requestees. The transaction account issuer may transfer the payment from a transaction account of the requestee to the consumer's transaction account.