Abstract: At least some embodiments are directed to an exemplary computer-based electronic activity tracking system that detects activity patterns receiving data values that represent at least one electronic activity. The exemplary electronic activity tracking system includes a detector of unsecure electronic activities that identifies electronic activity patterns performed by a user or non-person entity. The detector of unsecure electronic activities utilizes unsupervised machine learning techniques to detect the electronic activity patterns. The detected electronic activity patterns correspond to unsecure or malicious electronic activities. The electronic activity tracking system outputs notifications indicative of identified unsecure or malicious activity patterns and identifies entities associated with such unsecure or malicious activity patterns. The exemplary electronic activity tracking system implements a graphical user interface operated from a client computing device.

Abstract: At least some embodiments are directed to an exemplary computer-based electronic activity tracking system that detects activity patterns receiving data values that represent at least one electronic activity. The exemplary electronic activity tracking system includes a detector of unsecure electronic activities that identifies electronic activity patterns performed by a user or non-person entity. The detector of unsecure electronic activities utilizes unsupervised machine learning techniques to detect the electronic activity patterns. The detected electronic activity patterns correspond to unsecure or malicious electronic activities. The electronic activity tracking system outputs notifications indicative of identified unsecure or malicious activity patterns and identifies entities associated with such unsecure or malicious activity patterns. The exemplary electronic activity tracking system implements a graphical user interface operated from a client computing device.

Abstract: With an offer server computer system: receiving a first digital image file; receiving a first mapping of product codes to audience segment identifiers; receiving a temporary price reduction offer dataset; mapping a target identifier for an end user device of a consumer to an audience segment identifier; in response to determining, based on the audience segment identifier, that the TPR offer dataset has a product code and a retailer identifier that map to the audience segment identifier, and an effective date value that includes a current date value, and the retailer identifier corresponds to a retailer location within a specified distance of a then-current location of the end user computing device: creating and storing a digital offer dataset comprising both the first digital image file and a second digital image file that presents data elements of the TPR offer dataset; causing transmission of the dataset to the end user device.

Abstract: According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

Abstract: According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

Abstract: Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.

Abstract: Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

Abstract: A crop baling implement includes a frame and a baling chamber attached to the frame. The baling chamber is configured to form crop material into a bale extending along a central longitudinal axis of the bale. An orbital support is attached to the frame rearward of the baling chamber. The orbital support is rotatable about a wrap axis and defines an open central region. The orbital support is positioned to receive the bale from the baling chamber and pass the bale through the open central region of the orbital support. A wrap roller is attached to and moveable with the orbital support. A drive is coupled to the orbital support and operable to rotate the orbital support and the wrap roller about the wrap axis to unroll wrap material around the bale as the bale moves through the open central region of the orbital support.

Abstract: The present invention relates to compounds of formula (I) or (II) pharmaceutically acceptable salts, solvates, tautomers, stereoisomers thereof, including enantiomers, diastereomers, racemic mixtures, mixtures of enantiomers, or combinations thereof, and pharmaceutical uses of the compounds.

Abstract: A consumer may initiate a transaction using a transaction account. The transaction account issuer may transmit a notification to the consumer that the transaction has been authorized. The consumer may select requestees with whom to split the transaction. The transaction account issuer may transmit notifications to requestees to request payment from the requestees. The transaction account issuer may transfer the payment from a transaction account of the requestee to the consumer's transaction account.

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Abstract: A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.

Abstract: A consumer may initiate a transaction using a transaction account. The transaction account issuer may transmit a notification to the consumer that the transaction has been authorized. The consumer may select requestees with whom to split the transaction. The transaction account issuer may transmit notifications to requestees to request payment from the requestees. The transaction account issuer may transfer the payment from a transaction account of the requestee to the consumer's transaction account.

Abstract: Methods and a system are described for generating a waveform for transmitting data over a channel divided into a plurality of adjacent frequency subcarriers. One method includes receiving a plurality of data bits, each destined for a different receiver of a plurality of receivers. For each received data bit, the method further includes coding the data bit using a unique spreading code of a first set of spreading codes to generate a corresponding group of multiple copies of a data symbol. Additionally, the groups of data symbols, corresponding to the plurality of data bits, are interleaved to generate a sequence of interleaved data symbols, and the sequence of interleaved data symbols is mapped to the plurality of adjacent frequency subcarriers to generate a waveform symbol.

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.