Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Abstract: According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: Embodiments are directed to a method of providing access verification for a system that includes activating a security control device, which is in communications with a host device. The method also includes having the security control device receiving a verification signal coming from outside the system while being locally-based, and comparing the verification signal to a table of stored criteria values. The device then chooses a response based on that comparison and sends an access determination signal based on the response.

Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.

Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.

Abstract: An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.

Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Abstract: Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.

Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.

Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Abstract: According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.

Abstract: A semiconductor device includes a semiconductor fin formed on a substrate, a first gate formed around the semiconductor fin, and a second gate formed around the semiconductor fin below the first gate and separated from the first gate.

Abstract: According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.

Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.