Abstract: Embodiments are directed to a method of providing access verification for a system that includes activating a security control device, which is in communications with a host device. The method also includes having the security control device receiving a verification signal coming from outside the system while being locally-based, and comparing the verification signal to a table of stored criteria values. The device then chooses a response based on that comparison and sends an access determination signal based on the response.

Abstract: Embodiments are directed to a method of providing access verification for a system that includes activating a security control device, which is in communications with a host device. The method also includes having the security control device receiving a verification signal coming from outside the system while being locally-based, and comparing the verification signal to a table of stored criteria values. The device then chooses a response based on that comparison and sends an access determination signal based on the response.

Abstract: A method of controlling transistors includes receiving a control signal, and controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of a core. A device for controlling transistors includes a core performing computational instructions, and a bias circuit receiving a control signal, the bias circuit controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of the core.

Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.

Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.

Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.

Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.

Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.

Abstract: Disclosed are embodiments of a radio frequency identification (RFID) authentication system and an associated authentication methodology. The embodiments incorporate an identification device (e.g., an identification badge, a key fob, etc.) with an embedded RFID tag. The embedded RFID tag is associated with a specific user and stores a private key generated as part of a public key-private key encryption scheme. The private key is read by an RFID reader and used to decode public key encrypted data stored within or accessible by a computer system (e.g., a desktop computer system, a laptop computer system, a personal digital assistant (PDA), a digital fax machine, wireless telephone, etc.). Thus, the embodiments provide a portable way to use public key-private key encryption scheme data anywhere using RFID technology.

Abstract: Disclosed is a self-contained hardware-based authentication system that incorporates different authentication protocols for access to soft and/or hard assets with different security levels. The system embodiments include the use of a RFID device that comprises dual RFID tags operating under different frequencies. Specifically, one RFID tag operates on a public frequency and, when activated, transmits an identifier encrypted using a public key. The other RFID tag operates on a private frequency and, when activated, transmits a private key that can be used to decrypt the encrypted identifier. Upon receipt by a processor (e.g., a local processor or security server) of a request for access to a specific asset, a security level for the specific asset is determined. Then, depending upon the particular security level (e.g., low, medium or high) different authentication protocols are instituted using the RFID device. Also disclosed are embodiments of an associated authentication methodology.

Abstract: Disclosed is a self-contained hardware-based authentication system that incorporates different authentication protocols for access to soft and/or hard assets with different security levels. The system embodiments include the use of a RFID device that comprises dual RFID tags operating under different frequencies. Specifically, one RFID tag operates on a public frequency and, when activated, transmits an identifier encrypted using a public key. The other RFID tag operates on a private frequency and, when activated, transmits a private key that can be used to decrypt the encrypted identifier. Upon receipt by a processor (e.g., a local processor or security server) of a request for access to a specific asset, a security level for the specific asset is determined. Then, depending upon the particular security level (e.g. low, medium or high) different authentication protocols are instituted using the RFID device. Also disclosed are embodiments of an associated authentication methodology.

Abstract: Disclosed are embodiments of a radio frequency identification (RFID) authentication system and an associated authentication methodology. The embodiments incorporate an identification device (e.g., an identification badge, a key fob, etc.) with an embedded RFID tag. The embedded RFID tag is associated with a specific user and stores a private key generated as part of a public key-private key encryption scheme. The private key is read by an RFID reader and used to decode public key encrypted data stored within or accessible by a computer system (e.g., a desktop computer system, a laptop computer system, a personal digital assistant (PDA), a digital fax machine, wireless telephone, etc.). Thus, the embodiments provide a portable way to use public key-private key encryption scheme data anywhere using RFID technology.