Patents by Inventor Shawn P. Fetterolf
Shawn P. Fetterolf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10559542Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.Type: GrantFiled: March 14, 2018Date of Patent: February 11, 2020Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Shawn P. Fetterolf, Chi-Chun Liu
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Publication number: 20190386646Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventors: Stephen P. Ayotte, Shawn P. Fetterolf, Adam J. McPadden, Timothy M. Sullivan
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Publication number: 20190346773Abstract: An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
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Patent number: 10429743Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include an electrical design necessary for the operation of the semiconductor circuit, and white space, which has no electrical design. The method may include inserting an optical design into the white space of the photomask design for the semiconductor circuit. The optical design may have known optical patterns for validating the semiconductor circuit design. In an embodiment of the invention, the optical design may be physically isolated from the electrical design. In another embodiment of the invention, the optical design may comprise one or more photomask layers and overlay the electrical design. In another embodiment of the invention, the optical design may comprise covershapes.Type: GrantFiled: November 30, 2017Date of Patent: October 1, 2019Assignee: International Business Machines CorporationInventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
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Patent number: 10389519Abstract: A method of controlling transistors includes receiving a control signal, and controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of a core. A device for controlling transistors includes a core performing computational instructions, and a bias circuit receiving a control signal, the bias circuit controlling the top and bottom gate biases of the transistors according to the control signal to normalize or randomize power drawn as observed outside of the core.Type: GrantFiled: September 30, 2016Date of Patent: August 20, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Shawn P. Fetterolf, Ali Khakifirooz
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Publication number: 20190163071Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include an electrical design necessary for the operation of the semiconductor circuit, and white space, which has no electrical design. The method may include inserting an optical design into the white space of the photomask design for the semiconductor circuit. The optical design may have known optical patterns for validating the semiconductor circuit design. In an embodiment of the invention, the optical design may be physically isolated from the electrical design. In another embodiment of the invention, the optical design may comprise one or more photomask layers and overlay the electrical design. In another embodiment of the invention, the optical design may comprise covershapes.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
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Publication number: 20190163857Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
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Patent number: 10249529Abstract: A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.Type: GrantFiled: December 15, 2015Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Nicolas Degors, Shawn P. Fetterolf, Ahmet S. Ozcan
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Patent number: 10243046Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.Type: GrantFiled: October 31, 2017Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Shawn P. Fetterolf, Ahmet S. Ozcan
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Patent number: 10200016Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.Type: GrantFiled: August 30, 2017Date of Patent: February 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen P. Ayotte, Shawn P. Fetterolf, Adam J. McPadden, Timothy M. Sullivan
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Publication number: 20180358955Abstract: A contactless readable programmable transponder to monitor chip join and method of use are disclosed. The method includes reading a frequency of an oscillator associated with a chip module. The method further includes correlating the frequency with a bond quality of the chip module.Type: ApplicationFiled: August 20, 2018Publication date: December 13, 2018Inventors: Stephen P. Ayotte, Shawn P. Fetterolf, Adam J. McPadden, Timothy M. Sullivan
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Publication number: 20180308807Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.Type: ApplicationFiled: March 14, 2018Publication date: October 25, 2018Applicant: International Business Machines CorporationInventors: Kangguo CHENG, Shawn P. FETTEROLF, Chi-Chun LIU
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Publication number: 20180308806Abstract: Various methods and structures for fabricating a semiconductor chip structure comprising a chip identification “fingerprint” layer. A semiconductor chip structure includes a substrate and a chip identification layer disposed on the substrate, the chip identification layer comprising random patterns of electrically conductive material in trenches formed in a semiconductor layer. The chip identification layer is sandwiched between two layers of electrodes that have a crossbar structure. A first crossbar in the crossbar structure is located on a first side of the chip identification layer and includes a first set of electrical contacts in a first grid pattern contacting the first side of the chip identification layer. A second crossbar in the crossbar structure is located on a second side of the chip identification layer and includes a second set of electrical contacts in a second grid pattern contacting the second side of the chip identification layer.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: Kangguo CHENG, Shawn P. FETTEROLF, Chi-Chun LIU
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Publication number: 20180300599Abstract: Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.Type: ApplicationFiled: April 12, 2017Publication date: October 18, 2018Inventors: SHAWN P. FETTEROLF, JIN-PING HAN, CHRISTIAN LAVOIE, PAUL S. MCLAUGHLIN, AHMET S. OZCAN, ROGER A. QUON
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Publication number: 20180160308Abstract: Embodiments are directed to a method of providing access verification for a system that includes activating a security control device, which is in communications with a host device. The method also includes having the security control device receiving a verification signal coming from outside the system while being locally-based, and comparing the verification signal to a table of stored criteria values. The device then chooses a response based on that comparison and sends an access determination signal based on the response.Type: ApplicationFiled: January 23, 2018Publication date: June 7, 2018Inventors: Kangguo Cheng, Shawn P. Fetterolf
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Publication number: 20180122807Abstract: A semiconductor device includes a semiconductor fin formed on a substrate, a first gate formed around the semiconductor fin, and a second gate formed around the semiconductor fin below the first gate and separated from the first gate.Type: ApplicationFiled: December 30, 2017Publication date: May 3, 2018Inventors: Brent Alan ANDERSON, Shawn P. FETTEROLF, Terence B. HOOK
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Publication number: 20180108659Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, a third VFET formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth VFET formed on the substrate and connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Inventors: Brent Alan ANDERSON, Shawn P. FETTEROLF, Terence B. HOOK
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Patent number: 9947747Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.Type: GrantFiled: March 10, 2016Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Shawn P. Fetterolf, Ahmet S. Ozcan
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Patent number: 9947664Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, a third VFET formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth VFET formed on the substrate and connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.Type: GrantFiled: October 14, 2016Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Alan Anderson, Shawn P. Fetterolf, Terence B. Hook
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Publication number: 20180102315Abstract: The surface area of a surface area-dependent semiconductor device is increased by providing a dielectric layer, removing portion(s) of the dielectric layer, resulting in recession(s), and forming surface area-dependent semiconductor device(s), a portion of the device being formed along a sidewall of one, or more, of the recession(s). The resulting semiconductor structure includes a dielectric layer having recession(s) therein, and surface area-dependent semiconductor device(s) having a portion thereof formed along a sidewall of the recession(s).Type: ApplicationFiled: October 11, 2016Publication date: April 12, 2018Inventors: Roderick Alan AUGUR, Roger A. QUON, Shawn P. FETTEROLF