Patents by Inventor Shay Benisty

Shay Benisty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11409466
    Abstract: In one embodiment, a method provides access to a data storage device from a host coupled to the data storage device. The host is running a plurality of virtual functions. The method includes receiving an inbound request to a memory of a storage device controller of the data storage device. The memory of the storage device controller includes a DRAM memory and a non-DRAM memory. Whether the inbound request is a CMB/PMR transaction request is determined. The CMB/PMR transaction request is scheduled. Whether the scheduled CMB/PMR transaction request is allowed is determined. The allowed CMB/PMR transaction request is issued toward the DRAM memory of the storage device controller.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: August 9, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Publication number: 20220245242
    Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel HAHN, Shay Benisty, Ariel Navon
  • Patent number: 11397699
    Abstract: A data storage device, such as a solid state drives (SSD), includes command completion interrupt coalescing. A controller of the data storage device includes one or more completion queues, each including interrupt coalescing protection logic. The interrupt coalescing protection logic detects that a head pointer or a tail pointer in a completion queue has not changed for a predetermined period of time. When the head and tail pointers have not changed for the predetermined period of time, the controller posts an interrupt to a host device.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: July 26, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Publication number: 20220229586
    Abstract: A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Inventors: Shay BENISTY, Judah Gamliel HAHN
  • Publication number: 20220229566
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives, and effective power management of the data storage device. The data storage device includes a controller, where the controller is configured to predict when a host device will send a command to enter a low power state, prepare the data storage device to enter the low power state, and receive a command to enter the low power state after the predicting and preparing. If the data storage device is idled for greater than a threshold value, then the data storage device prepares to transition to a low power state but will wait to enter the lower power state until receiving a request from a host device.
    Type: Application
    Filed: February 25, 2021
    Publication date: July 21, 2022
    Inventors: Shay BENISTY, Judah Gamliel HAHN, Ariel NAVON
  • Publication number: 20220229593
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), specifically utilizing the data storage device memory in the execution of host commands. A controller is configured to receive a command pointer or a data chunk from a host device, mark a destination used for the command pointer or the data chunk, determine whether a last chunk of the command pointer or the data chunk has been received, and determine whether the command pointer or the data chunk uses an illegal combination of locations after determining that the last chunk of the command pointer has been received. The controller is further configured to return an error message to the host device upon determining that the command pointer or the data chunk uses an illegal combination of locations.
    Type: Application
    Filed: February 25, 2021
    Publication date: July 21, 2022
    Inventors: Amir SEGEV, Shay BENISTY
  • Patent number: 11392320
    Abstract: A method and apparatus for providing accurate command aging in a data storage device. A host provides multiple doorbell requests for the same command queue and a timestamp is saved for each request. When the storage device fetches the commands associated with the requests, the commands are all given the value of the timestamp associated with the requests and placed into the command queue and the aging algorithm of the storage device ages the commands. In an alternate embodiment, the commands may be assigned timestamps based on statistical values such as an average value, between the first and last doorbell request timestamps.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 19, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Publication number: 20220221997
    Abstract: Systems and methods for allocating storage based on aggregate performance of duplicate data are described. A number of duplicates of a host data unit in a storage medium may be determined, such as by a storage device and/or host device. Operation parameters for the duplicate host data may be aggregated into aggregate operation parameters. The aggregate operation parameters may be used to allocate storage in the storage medium, such as by determining target duplicate numbers and performance thresholds for deduplication and tiering decisions. Duplicate host data units may be stored, moved, or deleted based on the aggregate operation parameters.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 14, 2022
    Inventors: Ariel Navon, Shay Benisty
  • Publication number: 20220221999
    Abstract: Systems and methods for deduplication of storage device encoded data are described. The storage device may initiate a deduplication process and determine a encoded target data block and at least one encoded comparison data block. The storage device may compare the encoded target data block to the encoded comparison data blocks to determine similarity values. Based on the similarity values, the storage device may determine duplicate data units and eliminate extra duplicate data units.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 14, 2022
    Inventors: Ariel Navon, Shay Benisty
  • Patent number: 11386006
    Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 12, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 11386203
    Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: July 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Shay Benisty, Ariel Navon
  • Patent number: 11385835
    Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 12, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 11385963
    Abstract: A method and apparatus for masking errors in a DRAM write are disclosed to perform a partial write request with an SSD controller. In embodiments, write data from a host is provided to the controller that is not aligned to the DRAM data. The controller issues a read command from the LBA of a data storage device, and a corresponding write command to write the data received from the host, prior to receipt of the read data, to perform a partial write. The read data is error corrected, and in the event an error is found in the read data, bytes containing an error are masked. The read data, including masked read data, and write data are merged to form partial write data, and written to the DRAM. In certain embodiments, the partial write data may be provided to a logic analyzer to assess the masked read data for debug analysis.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 12, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Adi Blum
  • Publication number: 20220214835
    Abstract: An adaptive-feedback-based read-look-ahead management system and method are provided. In one embodiment, a method for stream management is presented that is performed in a storage system. The method comprises performing a read look ahead operation for each of a plurality of streams; determining a success rate of the read look ahead operation of each of the plurality of streams; and allocating more of the memory for a stream that has a success rate above a threshold than for a stream that has a success rate below the threshold. Other embodiments are provided.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky
  • Patent number: 11379031
    Abstract: An apparatus includes memory arrays and a power-performance-endurance manager module. The power-performance-endurance manager module stores a power-endurance state descriptor data structure, which includes endurance levels associated with power-endurance modes. The manager module dynamically configures the apparatus to operate the memory arrays according to one of the power-endurance modes based on a desired endurance level.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Eran Sharon, Shay Benisty
  • Patent number: 11372543
    Abstract: The present disclosure generally relates to scheduling zone-append commands for a zoned namespace (ZNS). Rather than taking zone-append commands in order or randomly, the zone-append commands can be scheduled in the most efficient manner consistent with the open zones of the ZNS. A zone priority is determined based upon the length of time that a zone has been open together with the zone status. Generally, the older the zone and/or the more full that a zone is increases the priority. Once the zone priority is established, the zone-append commands are scheduled to ensure the zone-append commands for the high priority zones are processed first so that the open zone can be filled prior to closing.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 28, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Alexander Bazarsky, Judah Gamliel Hahn
  • Patent number: 11366749
    Abstract: A storage system has a volatile memory, a non-volatile memory, and a controller. The controller of the storage system can implement various mechanisms for improving random read performance. These mechanisms include improved read prediction cache management, using a pattern length for read prediction, and a time-based enhancement for read prediction. Each of these mechanisms can be used alone on in combination with some or all of the other mechanisms.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: June 21, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Eran Sharon
  • Publication number: 20220187369
    Abstract: A circuit debug apparatus for debugging an integrated circuit that causes a functional fault may include a processor configured to extract a scan pattern of a scan chain of the integrated circuit while the integrated circuit is in a scan mode. The scan pattern includes a plurality of logic states for a corresponding plurality of logic circuits of the integrated circuit. The processor may also be configured to apply a modified scan pattern to the integrated circuit while the integrated circuit is in the scan mode, where the modified scan pattern includes a test pattern configured to eliminate the functional fault. The processor may be further configured to determine whether the integrated circuit with the modified scan pattern produces the functional fault while the integrated circuit is in a functional mode.
    Type: Application
    Filed: February 24, 2021
    Publication date: June 16, 2022
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20220179593
    Abstract: Aspects of the present disclosure generally relate to data storage devices and related methods that use secure host memory buffers and low latency operations. In one aspect, a controller is configured to fetch a command from a host device, and fetch entry data from a host memory buffer (HMB) of the host device in response to the command from the host device. The HMB is utilized in place of DRAM in the controller so that the data storage device is DRAM-less. In one embodiment, the entry data includes a logical to physical (L2P) address. The controller is also configured to fetch read data from the one or more memory devices using the entry data, conduct a validity check of the entry data fetched from the HMB simultaneously with the fetching of the read data from the one or more memory devices, and transmit validity result data to the host device.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventor: Shay BENISTY
  • Publication number: 20220179571
    Abstract: The present disclosure generally relates to data storage devices and related methods that use secure host memory buffers (HMBs) and low latency operations. A controller of the data storage device is configured to access the HMB, where the HMB stores a Merkle Tree. When the HMB is initialized, the controller determines a number of hash levels of the Merkle Tree. Each hash level of the Merkle Tree comprises one or more hashes. When storing location data in a target data block of the Merkle Tree, the controller is configured to initialize only the hashes along a path between a top hash and the target data block. Each hash along the path has a non-initialized hash coupled to a common hash. The non-initialized hash is programmed with a non-initialized bit, such that only the relevant hashes and data blocks are initialized.
    Type: Application
    Filed: March 23, 2021
    Publication date: June 9, 2022
    Inventors: Shay BENISTY, Ishai ILANI