Abstract: A data storage device and method for preventing data loss during an ungraceful shutdown are provided. In one embodiment, a data storage device is provided comprising a volatile memory; a non-volatile memory; and a controller. The controller is configured to detect an ungraceful shutdown; and in response to detecting the ungraceful shutdown: generate a reduced set of parity bits for data stored in the volatile memory, wherein the reduced set of parity bits comprises fewer parity bits than a full set of parity bits used in a graceful shutdown; and store the data and the reduced set of parity bits in the non-volatile memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device whose controller is configured to apply a hash function to a logical address specified in a received host request to obtain a first portion of the corresponding physical address (e.g., the channel number or channel and die numbers). This feature of the controller enables the L2P table stored in the DRAM associated with the controller to have physical-address entries that contain therein only complementary second portions of the physical addresses, but not the first portions. Such shorter physical-address entries in the L2P table enable a corresponding beneficial reduction in the size of the DRAM and can further be leveraged to have optimized and aligned access to the L2P table in the DRAM.

Abstract: A data storage device and method for file-based interrupt coalescing are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to execute a plurality of read commands read from a submission queue in a host; write a plurality of completion messages to a completion queue in the host; and coalesce interrupts to inform the host that plurality of completion messages were written to the completion queue; wherein the submission queue and the completion queue are dedicated to read commands from a host application and are separate from a submission queue and a completion queue for read and write commands from an operating system of the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relates to detecting command identification (CID) collisions in host commands. Host commands stored in submission queues are supposed to have unique CIDs. The host device selects the CID and attaches the CID to the command. Once the command is executed, the host device may reuse the CID. Sometimes, the host device reuses a CID before a command already using the CID is executed, which is a collision. Rather than search all CIDs to find a collision, redundancy bits can be created for each command, and the redundancy can be the same for multiple pending commands. The redundancy bits can be checked first to see if there is a match, followed by comparing CIDs for only those commands that have matching redundancy bits. In so doing, CID collisions are detected earlier and easier.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a plurality of fetch requests, determine a first number of requests, second number of requests, and a third number of requests of the plurality of fetch requests, and balance an execution of the first number of requests, the second number of requests, and the third number of requests so that a first ratio of the data requests to the PRP requests and a second ratio of the data requests to the HMB requests is about 1. The plurality of fetch requests includes PRP requests, HMB requests, and data requests. The first number of requests corresponds to a number of the PRP requests. The second number of requests corresponds to a number of the HMB requests. The third number of requests corresponds to a number of the data requests.

Abstract: A data storage device includes a memory device, an always on (AON) application specific integrated circuit (ASIC), and a controller coupled to the memory device and the AON ASIC. When the data storage device enters a low power state, the controller generates and stores security data associated with context data in a power management integrated circuit (PMIC). The context data is stored in both the memory device and a host memory buffer (HMB). A location of the context data in the HMB is stored in the PMIC with the security data. When the data storage device exits the low power state, the address stored in the PMIC is utilized to retrieve the context data from the HMB. The retrieved context data is verified against the security data by the controller.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a shutdown notification, fetch one or more command identifiers from a submission queue of a host device, generate error indications for the one or more command identifiers, and send a completion message, including the generated error indication, for each of the one or more command identifiers to the host device. The controller is further configured to push non-processed pending commands to a completion finite state machine, where the controller generates an error indication for each of the non-processed pending commands and sends a completion message, including the generated error indication, for each of the non-processed pending commands to the host device. While the controller is fetching command identifiers and pushing non-process commands, the controller is configured to continue processing processed commands in parallel.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive new debug information, determine that a debug buffer does not have any available free entries for the new debug information, compare the priority information to a lowest priority information of old debug information stored in the debug buffer, remove a most recent old debug information that has a lowest priority information from the debug buffer, and place the new debug information and corresponding priority information in the debug buffer.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to deliver a continuous DQS signal, determine whether a fill rate of a write buffer or an emptying rate of read buffer is sufficient to continuously send user data to the memory device or from the memory device, evaluate timing for sending or receiving the user data, and transfer data to or from the memory device continuously with the DQS signal. The data sent to the memory device includes the user data and garbage data, where the user data and the garbage data are separately transferred. The data received from the memory device includes user data that is sampled and user data that is not sampled, where the user data that is sampled and the user data that is not sampled are separately received.

Abstract: A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.

Abstract: The present disclosure generally relates to reducing boot latency of memory devices in a dual boot system. The boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized.

Abstract: The present disclosure generally relates to utilizing a port scheduler within a data storage device controller to schedule data transfers and determine which port should be utilized for each data packet transferred. The data storage device comprises a multi-port system on a host interface. The port scheduler can consider the following factors for example: link workload, idle time for each port, link power state, throughput for each port, speed of each link, priority of data transfer, and quality of service (QoS). Based upon an analysis of one or more of the factors, the port scheduler can transfer data on a port that is not associated with the data to ensure efficient multi-port usage.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives. The data storage device includes a volatile memory, a non-volatile storage unit, and a controller. The data storage device further includes a plurality of virtual functions, where at least one of the virtual functions is only accessible by the data storage device and the remainder of the virtual functions are accessible by both the data storage and a host device. At least one of the virtual functions may be dedicated to completing data storage device storage management operations.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command from a host device to read data from the memory device, fetch the read data from the memory device, check metadata associated with the read data, determine if the metadata corresponds to the read command, and provide modified read data to the host device when the metadata does not correspond to the read command. The modified read data may be encrypted read data, corrupted read data, or read data that is replaced with debug information. When the host device receives data that is different than the read data that is requested, the modified read data may be unreadable to the host device so that unprivileged access to the read data may be avoided.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a hint calibration operation is needed, select a first hint mode out of a plurality of hint modes, generate one or more hints based on a selected hint mode, and select a hint mode based on one or more of a performance, quality of service, and power consumption of the data storage device. The controller is further configured to iterate through the plurality of hint modes during the hint calibration operation and operate based on the selected hint mode until the controller determines that another hint calibration operation is needed.

Abstract: The present disclosure generally relates to efficient execution of compare commands. Reads from the memory device for the compare commands are scheduled. Available chunks of data is received from the memory device, and the corresponding data is received from the host device. The data is compared. If the data does not match, the remaining reads are cancelled, and a compare completion is placed in the completion queue indicating a failed compare command. If all of the data matches, then a compare completion is placed in the completion queue indicating a successful compare command. Read transfers from the host device are scheduled based on availability of read data from the memory device side. By doing so, less buffers are needed to hold the data internally until both chunks of data are available. In so doing, synchronization between read data availability and retrieving data from the host device is synchronized.

Abstract: The present disclosure generally relates to utilizing improved DL training models stored in non-volatile memory to optimize data transfer and storage. The proposed system would identify workloads of DNN training and occasionally check the difference rate between successive data transfers (representing successive training iterations of the model). Comparing the difference rate to given thresholds could indicate “recommendation-system” typical use case. In such a case the NAND operating system would apply systematic compression of the data by saving only the changed parameters between successive iteration cycles (“batches”). The host may indicate the checkpoint storage configuration of the training model (every iteration, every several iterations etc. . . . ) and other elements. The system may be efficiently utilized combining the NAND based DNN training interface, adding the checkpoint configuration information to the dedicated interface.

Abstract: A data storage device and method for securely storing and retrieving data at a data storage device. The disclosure includes a reverse encryption where a decryption function is applied to plaintext data to generate ciphertext data. Conversely, the disclosure includes applying an encryption function to ciphertext data to generate plaintext data. This involves using an encryption function that is inverse, and symmetric, to the decryption function. In some specific examples, this includes sharing cryptography engines for securing user data in a storage medium and securing device management data in host memory.

Abstract: A method and system for maintaining coherency between DMA and NVMe data paths are disclosed. As DMA requests are received in the PMR region, a device controller will translate these into NVMe commands with a dedicated queue that is hidden from a host that has higher priority than the corresponding host (NVMe) commands. The payload returned from an internally executed NVMe command is stored in a buffer used to complete the DMA request. As memory reads are submitted, the controller will mark corresponding LBA ranges for overlap, ensuring coherency between these reads and writes from other queues. Since the internal PMR queue has a higher priority than host-facing queues (e.g., NVMe), and the PMR is read-only, read coherency against host writes to the same region may be achieved.

Abstract: The present disclosure generally relates to utilizing a port scheduler within a data storage device controller to schedule data transfers and determine which port should be utilized for each data packet transferred. The data storage device comprises a multi-port system on a host interface. The port scheduler can consider the following factors for example: link workload, idle time for each port, link power state, throughput for each port, speed of each link, priority of data transfer, and quality of service (QoS). Based upon an analysis of one or more of the factors, the port scheduler can transfer data on a port that is not associated with the data to ensure efficient multi-port usage.