Abstract: The present disclosure generally relates to efficient data transfer. Rather than processing each command, the data storage device fetches part of the host buffers and then makes a determination regarding the attributes of the fetched buffers. Upon the determination, the command is classified as optimized, not-optimized, or somewhere in between. Optimized commands are permitted to retrieve data out of order while non-optimized commands remain in a strict in order data retrieval process. In between commands can be processed with some out of order data retrieval. In so doing, data transfers are effectively managed and optimized data by taking into account the current attributes of the host buffers per command.

Abstract: A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.

Abstract: A data storage device and method for multi-level conditional prediction of future random read commands are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a random read command from a host, wherein the received random read command is associated with a stream; predict a next stream to be received from the host; and predict a next random read command to be received from the host based on the received random read command and the predicted next stream. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.

Abstract: The present disclosure generally relates to host memory buffer (HMB) cache management. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

Abstract: The present disclosure generally relates to a non-volatile memory express (NVMe) dual port controller occupying less real estate on an application specific integrated circuit (ASIC). Rather than utilizing separate NVMe modules in the controller, with each module dedicated to a single port, the dual ports can share the same module. The host device believes that there are dedicated module resources because the module has two NVMe registers to provide the host device with the feeling that there are dedicated modules. Additionally, an interconnect between the ports and the registers contributes to providing the host device the feeling that there are dedicated modules. Furthermore, the rather than losing the capabilities of a second module when operating in single port mode, all of the capabilities of the only module are available when operating in either single port mode or dual port mode.

Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device and method for prediction-based improved power-loss handling. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to predict a probability of an ungraceful shutdown of the data storage device; determine whether the probability is greater than a threshold; and in response to determining that the probability is greater than the threshold, reduce a risk of data loss that would occur in response to the ungraceful shutdown of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.

Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.

Abstract: The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.

Abstract: A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device comprises a first memory, a second memory, and a controller. The first memory has a faster access time than the second memory. The controller is configured to store host-initialization code in the first memory, store a copy of the host-initialization code in the second memory, determine that the copy of the host-initialization code should be designated as the main version of the host-initialization code, and relocate the copy of the host-initialization code to the first memory, which makes the copy of the host-initialization code the main version of the host-initialization code that is accessed to boot-up the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a hint calibration operation is needed, select a first hint mode out of a plurality of hint modes, generate one or more hints based on a selected hint mode, and select a hint mode based on one or more of a performance, quality of service, and power consumption of the data storage device. The controller is further configured to iterate through the plurality of hint modes during the hint calibration operation and operate based on the selected hint mode until the controller determines that another hint calibration operation is needed.

Abstract: The present disclosure generally relates to an efficient manner of fetching data for write commands. The data can be fetched prior to classification, which is a fetch before mode. The data can alternatively be fetched after classification, which is a fetch after mode. When the data is fetched after classification, the write commands are aggregated until sufficient data associated with any command is split between memory devices. When in fetch before mode, the data should properly align such that data associated with any command is not split between memory devices. Efficiently toggling between the fetch before and fetch after modes will shape how writes are performed without impacting latency and bandwidth without significantly increasing write buffer memory size.

Abstract: The present disclosure generally relates to detecting command identification (CID) collisions in host commands. Host commands stored in submission queues are supposed to have unique CIDs. The host device selects the CID and attaches the CID to the command. Once the command is executed, the host device may reuse the CID. Sometimes, the host device reuses a CID before a command already using the CID is executed, which is a collision. Rather than search all CIDs to find a collision, redundancy bits can be created for each command, and the redundancy can be the same for multiple pending commands. The redundancy bits can be checked first to see if there is a match, followed by comparing CIDs for only those commands that have matching redundancy bits. In so doing, CID collisions are detected earlier and easier.

Abstract: A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.