Patents by Inventor Shekar Mallikarjunaswamy

Shekar Mallikarjunaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120273879
    Abstract: In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
    Type: Application
    Filed: March 30, 2012
    Publication date: November 1, 2012
    Inventors: Shekar Mallikarjunaswamy, John Chen, YongZhong Hu
  • Publication number: 20120273878
    Abstract: The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts the source region and a body region. A source contact is in electrical communication with said source region and a drain contact in electrical communication with said drain region, with said source and drain contacts being disposed on opposite sides of said gate channel.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 1, 2012
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20120235232
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 20, 2012
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Publication number: 20120187481
    Abstract: A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region; and a drain drift region formed in the semiconductor layer. The planar gate forms a lateral channel in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel in the body region along the sidewall of the first trench between the source region and the semiconductor layer.
    Type: Application
    Filed: April 5, 2012
    Publication date: July 26, 2012
    Applicant: Alpha & Omega Semiconductor, Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 8218276
    Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: July 10, 2012
    Assignee: Alpha and Omega Semiconductor Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 8212329
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Grant
    Filed: November 6, 2010
    Date of Patent: July 3, 2012
    Assignee: Alpha and Omega Semiconductor Inc.
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Patent number: 8174070
    Abstract: A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: May 8, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20120086499
    Abstract: A bidirectional switch device includes a main pass field effect transistor (FET) connected to an input node and an output node. A body region of the first main pass transistor is tied to a voltage substantially halfway between the voltage at the input node side of the first main pass transistor and the voltage at the output node side of the transistor when the first main pass transistor is in an ON state.
    Type: Application
    Filed: February 24, 2011
    Publication date: April 12, 2012
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Mohammad Suhaib Husain, Shekar Mallikarjunaswamy
  • Patent number: 8098466
    Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: January 17, 2012
    Assignee: Alpha and Omega Semiconductor Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20110267724
    Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes' a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage.
    Type: Application
    Filed: April 26, 2011
    Publication date: November 3, 2011
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20110180845
    Abstract: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.
    Type: Application
    Filed: April 5, 2011
    Publication date: July 28, 2011
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20110127602
    Abstract: A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7919817
    Abstract: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: April 5, 2011
    Assignee: Alpha & Omega Semiconductor Ltd.
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20110049623
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Application
    Filed: November 6, 2010
    Publication date: March 3, 2011
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Patent number: 7851314
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: December 14, 2010
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Patent number: 7843019
    Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: November 30, 2010
    Assignee: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Martin Alter
  • Publication number: 20090283831
    Abstract: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 19, 2009
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20090273028
    Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes: Lower device bulk layer. Upper source and upper drain region both located atop lower device bulk layer. Both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer. Both upper drain and upper body region are shaped to form a drain-body interface. The drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region. Gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Inventors: Shekar Mallikarjunaswamy, Amit Paul
  • Publication number: 20090268361
    Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.
    Type: Application
    Filed: June 30, 2009
    Publication date: October 29, 2009
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7608907
    Abstract: An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS that allows gate control over Schottky forward current. Integrating the Schottky diode into the drain of the depletion mode LDMOS forms the device structure.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: October 27, 2009
    Assignee: Micrel, Inc.
    Inventor: Shekar Mallikarjunaswamy