Patents by Inventor Shekar Mallikarjunaswamy

Shekar Mallikarjunaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090115018
    Abstract: A transient voltage-suppressing (TVS) device supported on a semiconductor substrate is applied to protect an electronic device from a transient voltage. The TVS device includes a clamp diode functions with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of the semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device. In an exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts. In another exemplary embodiment, the clamp diode further surrounded by a P-well and the P-well is formed on top of a P?/P+ substrate layer disposed above the insulator layer.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7485549
    Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: February 3, 2009
    Assignee: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Martin Alter
  • Publication number: 20070001004
    Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
    Type: Application
    Filed: August 31, 2006
    Publication date: January 4, 2007
    Inventors: Shekar Mallikarjunaswamy, Martin Alter
  • Publication number: 20070001240
    Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
    Type: Application
    Filed: August 31, 2006
    Publication date: January 4, 2007
    Inventors: Shekar Mallikarjunaswamy, Martin Alter
  • Patent number: 7145206
    Abstract: A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasitic bipolar transistor having the effect of reducing substrate conduction caused by a forward biased drain to body junction.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: December 5, 2006
    Assignee: Micrel, Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7145211
    Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: December 5, 2006
    Assignee: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Martin Alter
  • Patent number: 7087973
    Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: August 8, 2006
    Assignee: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Martin J. Alter, Charles L. Vinn
  • Publication number: 20060145185
    Abstract: An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS that allows gate control over Schottky forward current. Integrating the Schottky diode into the drain of the depletion mode LDMOS forms the device structure.
    Type: Application
    Filed: January 6, 2005
    Publication date: July 6, 2006
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7064407
    Abstract: A JFET controlled Schottky barrier diode includes a p-type diffusion region integrated into the cathode of the Schottky diode to form an integrated JFET where the integrated JFET provides on-off control of the Schottky barrier diode. The p-type diffusion region encloses a portion of the forward current path of the Schottky barrier diode where the p-type diffusion region forms the gate of the JFET and the enclosed portion of the forward current path forms the channel region of the JFET. By applying a reverse biased potential to the gate of the JEFT with respect to the anode of the Schottky diode, the forward current of the Schottky diode can be pinched off, thereby providing on-off control over the Schottky diode forward current.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: June 20, 2006
    Assignee: Micrel, Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20060012003
    Abstract: In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
    Type: Application
    Filed: July 13, 2004
    Publication date: January 19, 2006
    Applicant: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Martin Alter
  • Publication number: 20050275027
    Abstract: Electrostatic discharge protection for integrated circuits, particularly for enhancing electrostatic discharge protection performance for Input-output cells and power supply clamps used in CMOS and BiCMOS IC technologies is described. A P-type, implantation region, or layer, referred to as “P-deep,” in both N-MOSFET and P-MOSFET devices is provided to enhance electrostatic discharge protection performance. Parasitic transistor gain is enhanced by providing the P-deep region subposing the drain contact. Exemplary embodiments for N-type and P-type MOSFETs, MOSFETs with surface diodes, MOSFETS with SCRs, and push-pull Input-output CMOS circuits are described.
    Type: Application
    Filed: September 9, 2003
    Publication date: December 15, 2005
    Applicant: MICREL, Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20050167753
    Abstract: IGBTs and circuits can be designed to improve the ability of circuits and systems to withstand ESD events. In addition pads can be designed to take advantage of the circuits and IGBTs to withstand and dissipate ESD events.
    Type: Application
    Filed: February 25, 2005
    Publication date: August 4, 2005
    Applicant: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Sohel Imtiaz
  • Publication number: 20050139958
    Abstract: An electrostatic discharge (ESD) protection circuit that includes an transistor with a gate electrode isolated from the semiconductor substrate. The transistor can be an insulated gate bipolar transistor (IGBT) connected between an integrated circuit (IC) pad and ground. The IGBT includes a parasitic thyristor that latches when the voltage at the pad exceeds a threshold level and does not turn off until the charge at the pad is dissipated, thereby preventing electrostatic damage to the IC.
    Type: Application
    Filed: March 10, 2005
    Publication date: June 30, 2005
    Applicant: Micrel, Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 6888710
    Abstract: An electrostatic discharge (ESD) protection circuit which includes an Insulated Gate Bipolar Transistor (IGBT), a collector clamp, and a resistor. The IGBT collector is coupled with a circuit pad, and the emitter is coupled to ground. The collector clamp is coupled with the pad and the IGBT gate, and the resistor is coupled with the IGBT emitter and gate. When the voltage at the pad is below the trigger voltage of collector clamp, the collector clamp remains in a blocking state, thus preventing the IGBT from conducting. At the onset of an ESD event, when a voltage greater than the trigger voltage of the collector clamp appears at the pad, the collector clamp conducts, causing current flow through the resistor, thus turning on the IGBT and latching a parasitic thyristor formed in the IGBT until the ESD charge is dissipated.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: May 3, 2005
    Assignee: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Sohel Imtiaz
  • Patent number: 6864537
    Abstract: An electrostatic discharge (ESD) protection circuit includes a transistor with a gate electrode isolated from the semiconductor substrate by a thick oxide, a collector clamp coupled with a pad and the gate electrode, and an emitter clamp coupled between the gate electrode and the emitter of the transistor. Until the pad voltage reaches a trigger voltage, the collector clamp does not conduct, thereby preventing the transistor from conducting. However, when the pad voltage reaches the trigger voltage, the collector clamp turns on and triggers the latching of a parasitic thyristor that exists in the structure of the transistor. The latched parasitic thyristor (and thus the transistor) begins to conduct and rapidly dissipates the charge at the pad.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: March 8, 2005
    Assignee: Micrel, Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 6861711
    Abstract: An electrostatic discharge (ESD) protection circuit that includes an transistor with a gate electrode isolated from the semiconductor substrate. The transistor can be an insulated gate bipolar transistor (IGBT) connected between an integrated circuit (IC) pad and ground. The IGBT includes a parasitic thyristor that latches when the voltage at the pad exceeds a threshold level and does not turn off until the charge at the pad is dissipated, thereby preventing electrostatic damage to the IC.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: March 1, 2005
    Assignee: Micrel, Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20050036251
    Abstract: An electrostatic discharge protection device connected in parallel with a trim-diode turns on during an electrostatic discharge event and conducts substantially all the current therefrom, yet remains inactive during diode trimming. An electrostatic discharge protection “snap-back” type device effectively turns on, diverting the electrostatic discharge current flow away from the trim-diode. Various exemplary embodiments are shown in both CMOS and Bi-CMOS technologies.
    Type: Application
    Filed: August 12, 2003
    Publication date: February 17, 2005
    Inventors: Shekar Mallikarjunaswamy, Charles Vinn
  • Publication number: 20050029582
    Abstract: A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasitic bipolar transistor having the effect of reducing substrate conduction caused by a forward biased drain to body junction.
    Type: Application
    Filed: September 9, 2004
    Publication date: February 10, 2005
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 6825531
    Abstract: An LDMOS transistor includes a body region, a source region, a conductive gate, an alignment structure and a drain region. The conductive gate is insulated from the semiconductor layer by a dielectric layer and overlies the body region. The source region is formed in the body region and is formed self-aligned to a first edge of the conductive gate. The alignment structure is formed adjacent a second edge, opposite the first edge, of the conductive gate. The alignment structure has a first edge in proximity to the second edge of the conductive gate. The drain region is formed in the semiconductor layer self-aligned to the second edge, opposite the first edge, of the alignment structure. The alignment structure can be formed in a polysilicon layer or a dielectric layer. The incorporation of the alignment structure in the LDMOS transistor enables self-aligned drain region or drain contact opening to be formed.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: November 30, 2004
    Assignee: Micrel, Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20040227194
    Abstract: In cellular MOSFET transistor arrays using a geometric gate construction, deleterious inherent capacitance induced by the construction is substantially reduced by the use of plugs in between adjacent source regions of transistor source rows and adjacent drain regions of transistor drain rows of the array. Embodiments using field oxide, thicker step gate oxide, dielectric materials in a floating gate construction, and shallow trench isolation region plugs are described.
    Type: Application
    Filed: April 21, 2004
    Publication date: November 18, 2004
    Inventor: Shekar Mallikarjunaswamy