Abstract: In cellular MOSFET transistor arrays using a geometric gate construction, deleterious inherent capacitance induced by the construction is substantially reduced by the use of plugs in between adjacent source regions of transistor source rows and adjacent drain regions of transistor drain rows of the array. Embodiments using field oxide, thicker step gate oxide, dielectric materials in a floating gate construction, and shallow trench isolation region plugs are described.

Abstract: A bipolar transistor includes an auxiliary diffusion region formed in the base region having a conductivity type opposite to the base region and being electrically coupled to the base region. Alternately, the auxiliary diffusion region can be formed in the collector region where the auxiliary diffusion region has a conductivity type opposite to the collector region and is electrically coupled to the collector region. The auxiliary diffusion region forms a secondary parasitic transistor in the bipolar transistor having the effect of suppressing parasitic bipolar conduction caused by a primary parasitic bipolar device associated with the bipolar transistor.

Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: IGBTs and circuits can be designed to improve the ability of circuits and systems to withstand ESD events. In addition pads can be designed to take advantage of the circuits and IGBTs to withstand and dissipate ESD events.

Abstract: An electrostatic discharge (ESD) protection circuit that includes an transistor with a gate electrode isolated from the semiconductor substrate. The transistor can be an insulated gate bipolar transistor (IGBT) connected between an integrated circuit (IC) pad and ground. The IGBT includes a parasitic thyristor that latches when the voltage at the pad exceeds a threshold level and does not turn off until the charge at the pad is dissipated, thereby preventing electrostatic damage to the IC.

Abstract: A bipolar transistor includes an auxiliary diffusion region formed in the base region having a conductivity type opposite to the base region and being electrically coupled to the base region. Alternately, the auxiliary diffusion region can be formed in the collector region where the auxiliary diffusion region has a conductivity type opposite to the collector region and is electrically coupled to the collector region. The auxiliary diffusion region forms a secondary parasitic transistor in the bipolar transistor having the effect of suppressing parasitic bipolar conduction caused by a primary parasitic bipolar device associated with the bipolar transistor.

Abstract: A diode-triggered NPN ESD protection device includes a P-Base region enclosing the emitter region of the NPN transistor for enhancing the reliability of the ESD protection device. The incorporation of the P-Base region encourages bulk transistor action and inhibits surface transistor action such that the reliability of the protection device is enhanced. In another aspect of the present invention, a trigger voltage control method is applied to a diode-triggered ESD protection device to extend the periphery length of the p-n junction of the trigger diode without increasing the size of the protection device. By extending the periphery length of the p-n junction, the trigger current generated by the trigger diode is increased so that the trigger voltage for the ESD protection device can be lowered, providing effective ESD protection. The periphery length is extended by using a shaped periphery, such as a corrugated periphery or a perforated periphery.

Abstract: A diode-triggered NPN ESD protection device includes a P-Base region enclosing the emitter region of the NPN transistor for enhancing the reliability of the ESD protection device. The incorporation of the P-Base region encourages bulk transistor action and inhibits surface transistor action such that the reliability of the protection device is enhanced. In another aspect of the present invention, a trigger voltage control method is applied to a diode-triggered ESD protection device to extend the periphery length of the p-n junction of the trigger diode without increasing the size of the protection device. By extending the periphery length of the p-n junction, the trigger current generated by the trigger diode is increased so that the trigger voltage for the ESD protection device can be lowered, providing effective ESD protection. The periphery length is extended by using a shaped periphery, such as a corrugated periphery or a perforated periphery.

Abstract: Systems and methods are disclosed for localized electrostatic discharge protection of integrated circuit input/output pads. The localized clamp is isolated from the main supply voltage clamp and coupled to the input/output pad through low-capacitance diodes.

Abstract: Systems and methods are disclosed for localized electrostatic discharge protection of integrated circuit input/output pads. The localized clamp is isolated from the main supply voltage clamp and coupled to the input/output pad through low-capacitance diodes.

Abstract: A semiconductor structure which protects against damages to an integrated circuit caused by electrostatic discharge (ESD) at a power supply pin includes a channel stop field plate coupled between a power supply terminal associated with the power supply pin and contacts to N-type substrate or N-wells formed in the semiconductor structure receiving the power supply voltage. The field plate functions to inhibit surface leakage current and is also used to introduce a resistance between the power supply pin and connections to N-wells or the N-substrate, thereby providing protection to the wells or substrate against damages caused by an ESD event. By exploiting an existing structure used in typical integrated circuit for ESD protection, ESD immunity of a semiconductor device can be enhanced without consuming additional silicon area.

Abstract: A current-limit circuit and a method of limiting current supplied to a load through a power transistor utilize a control transistor that is selectively activated to a conducting state to limit the current conducted through the power transistor in response to a predefined condition. The predefined condition may be a short-circuit condition or an over-current condition. The configuration and operation of the control transistor are such that, when the control transistor is in a conducting state, the current conducted through the power transistor is limited by the structural ratio of the two transistors. However, during normal operating conditions when the control transistor is deactivated to a non-conducting state, the control transistor does not degrade the performance of the power transistor. In a first embodiment, the current-limit circuit is configured to provide protection from a short-circuit condition.