Abstract: The disclosure provides a grid-tied power generation system and a grid-tied power fluctuation suppression device and method thereof. The system includes a first direct current source, an inverter, and a power grid. The device includes a second direct current source, connected to a direct current side of the inverter; and a power allocation unit, respectively connected to the second direct current source and the inverter. The power allocation unit obtains a power reference value of the first direct current source and a power feedback value of the first direct current source, calculates an alternating current power reference value and a power reference value of the second direct current source according to the power reference value and the power feedback value, and controls the inverter through the alternating current power reference value and controls the second direct current source through the power reference value of the second direct current source.

Abstract: A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

Abstract: A method for performing sidelink transmission over an unlicensed band is provided. The method includes performing a first-type listen-before-talk (LBT) process on the unlicensed band to obtain a channel occupancy time (COT) for the sidelink transmission. The first-type LBT process includes a random backoff process. Duration of the random backoff process is determined by a randomly generated LBT counter. The method further includes determining, based on a result from a sensing operation performed on the unlicensed band within a sensing window, a plurality of candidate sidelink resources on the unlicensed band within a sidelink resource selection window. The method also includes selecting, based on a completion time point of the first-type LBT process, a sidelink resource from the plurality of candidate sidelink resources. The method also includes performing the sidelink transmission within the obtained COT on the selected sidelink resource.

Abstract: A method can include determining candidate sidelink resources by a user equipment (UE) for sidelink transmission on an unlicensed band from a sidelink resource selection window based on results of a sensing operation on the unlicensed band during a sidelink sensing window, selecting a sidelink resource from the candidate sidelink resources, performing a listen-before-talk (LBT) process on the unlicensed band to obtain a channel occupancy time (COT), and performing a sidelink transmission within the COT using the first sidelink resource. The selection of the sidelink resource can be based on an LBT time that is a predicted duration of a random backoff process of the first LBT process. Also, the first sidelink resource can be selected from the candidate sidelink resources without randomization.

Abstract: A method can include determining candidate sidelink resources by a user equipment (UE) for sidelink transmission on an unlicensed band from a sidelink resource selection window based on results of a sensing operation on the unlicensed band during a sidelink sensing window, selecting a sidelink resource from the candidate sidelink resources, performing a listen-before-talk (LBT) process on the unlicensed band to obtain a channel occupancy time (COT), and performing a sidelink transmission within the COT using the first sidelink resource. The selection of the sidelink resource can be based on an LBT time that is a predicted duration of a random backoff process of the first LBT process. Also, the first sidelink resource can be selected from the candidate sidelink resources without randomization.

Abstract: A charging system utilizing energy storage multiplication is provided. An energy storage battery pack of the charging system is directly connected to a DC power transmission bus. When the charging request is initiated by the charging device, the charging device takes the power from the DC bus, the AC-DC converter and DC-DC converter connected to the energy generation device work as the energy source to deliver power to the DC bus, the power goes through the DC bus to the charging device, and the rest of the power goes to the energy storage device or goes out form the energy storage device when the charring power is higher than total energy from all other converters. The high C rate discharging of the energy storage device means high power capacity during discharging, this can provide much high power than AC-DC converter to fulfill the requirement of charging device.

Abstract: A molding device and an injection molding method thereof are provided. The molding device includes a first mold, a second mold and a sealing ring. The first mold includes a first body and at least one slide. The at least one slide is movably and detachably disposed on the first body, and has an undercut. The injection molding method includes operations of: engaging the first mold with the second mold of the molding device; filling a mold cavity defined by the first mold and the second mold with a gas, wherein the gas is blocked by the sealing ring disposed between the first mold and the second mold; injecting a molding material into the mold cavity; and opening the first mold and the second mold of the molding device.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: The disclosure provides a grid-tied power generation system and a grid-tied power fluctuation suppression device and method thereof. The system includes a first direct current source, an inverter, and a power grid. The device includes a second direct current source, connected to a direct current side of the inverter; and a power allocation unit, respectively connected to the second direct current source and the inverter. The power allocation unit obtains a power reference value of the first direct current source and a power feedback value of the first direct current source, calculates an alternating current power reference value and a power reference value of the second direct current source according to the power reference value and the power feedback value, and controls the inverter through the alternating current power reference value and controls the second direct current source through the power reference value of the second direct current source.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: A scanner is provided and includes a load bearing element, a scan assembly, a transparent plate and a casing. The load bearing element includes a support element and a base. The support element is disposed on the base and surrounds the base. The scan assembly is configured to perform a scan operation and is disposed on the base. The transparent plate is disposed on the support element and is configured to bear an object. The casing includes a first casing part and a second casing part. The second casing part includes a bottom plate and at least one cylinder. The at least one cylinder is disposed on the bottom plate. The load bearing element is disposed on the at least one cylinder, and is located between the first casing part and the second casing part. A first buffer space is formed between the base and the bottom plate.

Abstract: A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps.

Abstract: A scanner is provided and includes a load bearing element, a scan assembly, a transparent plate and a casing. The load bearing element includes a support element and a base. The support element is disposed on the base and surrounds the base. The scan assembly is configured to perform a scan operation and is disposed on the base. The transparent plate is disposed on the support element and is configured to bear an object. The casing includes a first casing part and a second casing part. The second casing part includes a bottom plate and at least one cylinder. The at least one cylinder is disposed on the bottom plate. The load bearing element is disposed on the at least one cylinder, and is located between the first casing part and the second casing part. A first buffer space is formed between the base and the bottom plate.

Abstract: A fixture is mounted on a work platform and contains: a first movable block, a second movable block, an actuation block, multiple resilient elements, multiple first connection blots, and a threaded bolt. The first movable block includes a first body having a first tilted face, a first defining portion, and a first clamping face. The second movable block includes a second body having a second tilted face, a second defining portion, and a second clamping face. The actuation block includes a third body having a third tilted face, a fourth tilted face, at least one first abutting portion, at least second abutting portion, and a coupling orifice. The third tilted face corresponds to the first tilted face and has a third defining portion, and the third tilted face has a fifth slide section, a sixth slide section, and a third stop section.

Abstract: A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps.

Abstract: A method of configuring a set of active cells among neighboring cells to reduce latency and interruption for inter-cell mobility is proposed. The set of active cells is an active set of cells among which UE can do fast cell switching. The set of active cells is configured by the network based on UE measurement report or network deployment information. UE maintains the configuration and can perform pre-synchronization to the configured active cells in downlink (DL) only or in both DL and uplink (UL). UE maintains the DL/UL synchronization with the active cells, and applies configuration once UE is indicated to switch to an active cell as the target cell. Because UE maintains the configuration and DL/UL timing of the target cell before receiving the cell-switch command, the mobility latency and interruption time for inter-cell mobility is reduced.

Abstract: An image detection method includes obtaining a facial image, and obtaining a frequency-domain image of the facial image and a spatial-domain feature of the facial image, the frequency-domain image being obtained by performing frequency-domain transformation on the facial image. The spatial-domain feature is obtained by performing feature extraction on the facial image. The method further includes performing feature extraction based on the frequency-domain image, to obtain a frequency-domain feature of the facial image, and fusing the spatial-domain feature and the frequency-domain feature by using an attention fusion network of a facial image detection model, to obtain a fused feature of the facial image. The method further includes obtaining a detection result of the facial image based on the fused feature, the detection result indicating whether the facial image is a forged facial image.

Abstract: A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

Abstract: A molding device and an injection molding method thereof are provided. The molding device includes a first mold, a second mold and a sealing ring. The first mold includes a first body and at least one slide. The at least one slide is movably and detachably disposed on the first body, and has an undercut. The injection molding method includes operations of: engaging the first mold with the second mold of the molding device; filling a mold cavity defined by the first mold and the second mold with a gas, wherein the gas is blocked by the sealing ring disposed between the first mold and the second mold; injecting a molding material into the mold cavity; and opening the first mold and the second mold of the molding device.

Abstract: An inverter parallel system and a zero feed-in control method for the inverter parallel system are provided. The system includes at least one first inverter, at least one second inverter, a load, an electrical grid, a controller, and an electrical parameter measuring device. The controller includes a system control module, and the first inverter includes an inverter control module. The system control module is configured to determine a battery power reference value of an energy storage battery according to an electrical grid current reference value and an electrical grid current sampling value. The inverter control module is configured to control the first inverter, such that a feed-in current flowing into the electrical grid side is zero, and the second inverter operates in a maximum power point tracking state. Therefore, in the system, zero feed-in control may be achieved without energy management and without communication between inverters.