Patents by Inventor Sheng-Chau Chen

Sheng-Chau Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10074612
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung
  • Patent number: 10050018
    Abstract: A method is provided. The method includes providing a first wafer having a plurality of first dummy pads exposed along a first surface of the first wafer. The first dummy pads contact a first metallization layer of the first water. The method also includes providing a second wafer having a plurality of second dummy pads exposed along a first surface of the second wafer. The second dummy pads contact a second metallization layer of the second wafer. The method also includes bonding the first wafer to the second wafer in a manner that the first surface of the first wafer contacts the first surface of the second wafer and the plurality of first dummy pads are interleaved with the plurality of second dummy pads but do not contact the plurality of second dummy pads.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Zhi-Yang Wang, Sheng-Chau Chen, Cheng-Hsien Chou
  • Patent number: 10043705
    Abstract: A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chang Chu, Yao-Wen Chang, Sheng-Chau Chen, Alexander Kalnitsky
  • Publication number: 20180158728
    Abstract: A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.
    Type: Application
    Filed: February 3, 2017
    Publication date: June 7, 2018
    Inventors: Yen-Chang Chu, Yao-Wen Chang, Sheng-Chau Chen, Alexander KALNITSKY
  • Publication number: 20180122844
    Abstract: The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Chih-Hui Huang
  • Patent number: 9960200
    Abstract: The present application relates to a method to simplify the scribe line opening filling processes, and to further improve the surface uniformity of the conductive pad fabrication process. A passivation layer is formed over a semiconductor substrate, and a scribe line opening is formed through the passivation layer and the semiconductor substrate. To fill the scribe line opening, a first dielectric layer is formed within the scribe line opening over the conductive pad and extending over the passivation layer. The first dielectric layer is formed by a selective deposition process such that the first dielectric layer is formed on the conductive pad at a deposition rate greater than that formed on the passivation layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai, Chih-Hui Huang
  • Publication number: 20180090348
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20180068965
    Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 8, 2018
    Inventors: Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu
  • Patent number: 9887182
    Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ju-Shi Chen, Cheng-Ying Ho, Chun-Chieh Chuang, Sheng-Chau Chen, Shih Pei Chou, Hui-Wen Shen, Dun-Nian Yaung, Ching-Chun Wang, Feng-Chi Hung, Shyh-Fann Ting
  • Publication number: 20180033749
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Sheng-Chau CHEN, Shih-Pei CHOU, Ming-Che LEE, Kuo-Ming WU, Cheng-Hsien CHOU, Cheng-Yuan TSAI, Yuer-Luen TU
  • Patent number: 9859323
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai, Sheng-Chan Li, Zhi-Yang Wang
  • Patent number: 9859326
    Abstract: Semiconductor devices, image sensors, and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a high dielectric constant (k) insulating material disposed over a workpiece, the high k insulating material having a dielectric constant of greater than about 3.9. A barrier layer is disposed over the high k insulating material. A buffer oxide layer including a porous oxide film is disposed between the high k insulating material and the barrier layer. The porous oxide film has a first porosity, and the barrier layer or the high k insulating material has a second porosity. The first porosity is greater than the second porosity.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Tung-Ting Wu, Cheng-Ta Wu, Chih-Hui Huang, Yeur-Luen Tu, Jhy-Jyi Sze
  • Publication number: 20170358620
    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai, Sheng-Chan Li, Zhi-Yang Wang
  • Patent number: 9842816
    Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu
  • Patent number: 9837291
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20170309603
    Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.
    Type: Application
    Filed: May 17, 2017
    Publication date: October 26, 2017
    Inventors: Ju-Shi Chen, Cheng-Ying Ho, Chun-Chieh Chuang, Sheng-Chau Chen, Shih Pei Chou, Hui-Wen Shen, Dun-Nian Yaung, Ching-Chun Wang, Feng-Chi Hung, Shyh-Fann Ting
  • Patent number: 9786619
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Shih-Pei Chou, Ming-Jhe Lee, Kuo-Ming Wu, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yeur-Luen Tu
  • Publication number: 20170287878
    Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 5, 2017
    Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
  • Publication number: 20170250160
    Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 31, 2017
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Zhi-Yang Wang, Sheng-Chau Chen, Cheng-Hsien Chou
  • Publication number: 20170243915
    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.
    Type: Application
    Filed: May 10, 2017
    Publication date: August 24, 2017
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai