Abstract: A system includes a primary coil, a series combination having a first conducting wire and a first capacitor coupled in series, a second conducting wire, and a secondary coil. A first end of the series combination is coupled to a first end of the primary coil. A first end of the second conducting wire is coupled to the first end of the primary coil. A second end of the second conducting wire is coupled to the second end of the series combination. A first end of the secondary coil is coupled to an output end.

Abstract: An evaluating system of paper manufacturing includes an evaluation apparatus of paper manufacturing and a fiber analysis device. The evaluation apparatus of paper manufacturing includes a database, an input unit, a processing unit, and a communication interface. The database stores a plurality of paper manufacturing parameters, a paper manufacturing corresponding function, and a paper forming corresponding function. The input unit is configured to receive an input related to the paper manufacturing parameters. The processing unit is electrically connected to the database and is configured to generate a suggested manufacturing recipe by using the paper forming corresponding function and the paper manufacturing corresponding function according to the input. The fiber analysis device is electrically or communicatively connected to the evaluation apparatus of paper manufacturing. The fiber analysis device is configured to analyze one or more fiber materials, a single-layer paper, and a paper product.

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

Abstract: A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.

Abstract: The present invention provides a vibration sensor, comprising a shell, a vibration plate, a back plate and a support elastic element, the shell includes a vibration cavity, which is equipped with a first opening end and a second opening end, and the vibration plate is movably set at the first opening end of the vibration cavity, the back plate is fixedly set at the second opening end of the vibration cavity, and is set at an interval opposite to the vibration plate, the support elastic element is located inside the vibration cavity, and the upper and lower ends of the support elastic element are elastically abutted between the vibration plate and the back plate, to drive the vibration plate to move along the axial direction of the vibration cavity, the vibration plate is made of rigid material, and only direct contact mechanical vibration can cause the vibration plate to vibrate.

Abstract: A neural network circuit includes an input neuron layer comprises a plurality of first neurons. A hidden neuron layer includes a plurality of second neurons, wherein each of the second neurons comprises a probabilistic bit having a time-varying resistance. The probabilistic bit is a magnetic tunnel junction structure comprises a pinned layer, a free layer, and a tunneling barrier layer between the pinned layer and the free layer. A weight matrix comprising a plurality of synapse units, each of the synapse units connecting one of the plurality of first neurons to a corresponding one of the plurality of first neurons.

Abstract: A directional coupler includes a main path, a coupling path, a first port, and a second port. The main path is used to propagate a first RF signal. The coupling path at least partially overlaps with the main path. The coupling path includes a first end, a second end, and at least one winding routed between the first end and the second end. The first port is coupled to the first end of the coupling path. The second port is coupled to the second end of the coupling path. At least one of the first port and the second port is located inside the at least one winding.

Abstract: There is provided a phase shifter having a phase shift region and a peripheral region, and including a first substrate, a second substrate and a dielectric layer between such two substrates; the first substrate includes a first dielectric substrate, a first electrode and a first auxiliary structure; the second substrate includes a second dielectric substrate, a second electrode and a second auxiliary structure; the phase shift region includes overlapping regions; the first electrode and the second electrode are located in the phase shift region, and have orthographic projections, on the first dielectric substrate, overlapped at least partially in the overlapping regions; the first auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the first dielectric substrate; the second auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the second dielectric substrate.

Abstract: A display detection device includes a panel, a detection board, and a detection adapter board. The panel is configured to display. The detection board is coupled to the panel, and is configured to input a detection signal. The detection adapter board is coupled to the panel, and is configured to respond to the detection signal to generate a detection result.

Abstract: A discrete-time filter includes a transconductance circuit, a switched-capacitor filter circuit, a first sampling capacitor, a second sampling capacitor, and a switch, where an output end of the transconductance circuit is coupled to a first node through the switched-capacitor filter circuit; both a first end of the first sampling capacitor and a first terminal of the switch are coupled to the first node; and both a second terminal of the switch and a second end of the first sampling capacitor are grounded. The second sampling capacitor is coupled to the switch such that sampling is implemented and negative feedback is provided by switching connection ends of the switch to adjust a feedback coefficient.

Abstract: An encrypted communication method and apparatus, a device, and a medium are disclosed. The method includes: a first protocol layer of a first party obtains a MAC address of a second party according to a data transmission request from an application layer, the data transmission request including an NLP address of the second party; the first protocol layer generates a first temporary key pair including a first temporary public key and a first temporary private key; the first protocol layer obtains a second temporary public key of the second party according to the first temporary public key; the first protocol layer generates a shared key according to the second temporary public key and the first temporary private key; the first protocol layer determines a data message, the data message carrying encrypted data obtained by encrypting using the shared key, and the receiver of the data message being the second party.

Abstract: An amplification circuit includes an amplifier, a first mirror-branch circuit, a second mirror-branch circuit, a first variable current source, a second variable current source, and an operation amplifier. The amplifier can receive an operation current and an input signal, and output the amplified input signal. The first mirror-branch circuit and the second mirror-branch circuit are coupled to the amplifier. The first variable current source is coupled to the first mirror-branch circuit and provides a first reference current. The second variable current source is coupled to the second mirror-branch circuit and provides a second reference current. The operation amplifier is coupled to the first mirror-branch circuit, the second mirror-branch circuit and the amplifier. The first reference current and the second reference current are related to the operation current.

Abstract: The present disclosure provides a single-channel test device. The single-channel test device includes a metal flange, and a waveguide-coaxial conversion structure and a first square straight waveguide which are disposed along a central axis of the metal flange and disposed on two opposite sides of the metal flange respectively, wherein in the case that a waveguide aperture of one end of the first square straight waveguide distal to the metal flange is placed on and is kept in close contact with a single antenna unit to be tested in a phased reflectarray to be tested, the single-channel test device is configured to test a scattering parameter of the antenna unit to be tested.

Abstract: Provided are compositions comprising chemically synthesized pseudaminic acid (Pse) conjugated to a carrier protein using the OPA chemistry, methods of using said compositions to stimulate immune responses in subjects and protect the vaccinated subjects from infections caused by Pse-producing A. baumannii.

Abstract: A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

Abstract: A micro light-emitting diode display panel and a micro light-emitting diode display device. A prism layer is provided with a void, which surrounds a light-emitting chip and is arranged axially symmetrically with respect to a center line of the light-emitting chip. Therefore, a distance between the light-emitting chip and the void in a transverse direction is equal to a distance between the light-emitting chip and the void in an oblique direction, and an angle at which a light ray emitted from the light-emitting chip is reflected at a contact surface between the prism layer and the void in the transverse direction is same as an angle at which a light ray emitted from the light-emitting chip is reflected at the contact surface in the oblique direction. Accordingly, a plane formed by the light-emitting chip and the contact surface is same as a tangential focal plane or a sagittal focal plane.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.