Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

Abstract: An electronic device includes: a substrate, a poly-silicon layer disposed on the substrate, a first metal layer disposed on the substrate, a first insulating layer disposed on the first metal layer, a second insulating layer disposed on the first insulating layer; and a second metal layer covering a part of the second insulating layer and electrically connected to the first metal layer. Wherein a thickness of the second insulating layer under the second metal layer is larger than a thickness of the second insulating layer uncovered with the second metal layer.

Abstract: An electronic apparatus with a two-way cable connection construction is provided. The electronic apparatus includes a casing kit and an electronic device. The casing kit includes a casing, a main circuit board and an auxiliary circuit board. The main circuit board and the auxiliary circuit board are disposed inside the casing. The auxiliary circuit board and the main circuit board are electrically connected to each other and non-coplanar with each other. When the electronic device is inserted into a mounting slot of the casing along a first direction, a mating electrical connector of the electronic device is connected to a first electrical connector of the auxiliary circuit board. When the electronic device is inserted into the mounting slot of the casing along a second direction opposite to the first direction, the mating electrical connector of the electronic device is connected to a second electrical connector of the auxiliary circuit board.

Abstract: A tongue depressor for facilitating the placement of a laryngeal mask is disclosed. The tongue depressor includes a flexible main body; the flexible main body is long and flat with a width W and a thickness D, wherein 1.5 cm<W<3.5 cm and 0.05 mm<D<2 mm. The flexible main body has a bent state and a straight state. With the above structure, when the flexible main body is put into the oral cavity of the human body in the straight state, an external force is applied to the flexible main body and then the flexible main body transitions from the straight state to the bent state such that the flexible main body depresses the tongue base to form a channel with the upper jaw of the human oral cavity, through which the laryngeal mask can enter the human pharynx.

Abstract: A thermocouple power generation unit, module, and device that generate electricity using a temperature difference, characterized by compact size and high efficiency. The thermocouple power generation unit comprises an insulating substrate, a cathode alloy section, a first insulating layer, an anode alloy section, a second insulating layer, a cathode conductive lead, and an anode conductive lead. The cathode and anode alloy portions respectively include multiple cathode and anode nanowires that are etched from cathode and anode alloy materials and arranged at equal intervals. A single pair of cathode and anode nanowires forms multiple power generation units, which are arranged in series, with their free ends respectively connected to the corresponding cathode and anode conductive leads. The connection points between the cathode and anode nanowires of the power generation units form multiple power generation points.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A power amplifier has an amplifying transistor, a first resistor, a bias circuit, a second resistor, and a compensation circuit. The amplifying transistor amplifies a radio frequency (RF) signal to output an amplified RF signal. A control end of the amplifying transistor receives the RF signal. The first resistor provides a first resistance, and a second end of the first resistor is coupled to the control end of the amplifying transistor. The bias circuit has a bias transistor and is coupled to a first end of the first resistor. The second resistor provides a second resistance less than the first resistance, and a second end of the second resistor is coupled to the control end of the amplifying transistor. The compensation circuit has a compensation transistor, and an output end of the compensation circuit is coupled to a first end of the second resistor.

Abstract: A semiconductor package includes a semiconductor component and a plurality of leads electrically connected to the semiconductor component. Each of the leads has a first surface, and has a second surface opposite from the first surface, with a solderable metal on the first surface and the second surface. The solderable metal has a first average thickness on the first surfaces, and has a second average thickness on the second surfaces. The second average thickness is 10 percent to 80 percent of the first average thickness. The semiconductor package is formed by concurrently electroplating the solderable metal on the first surfaces and on the second surfaces. The solderable metal is electroplated on the first surfaces with a first average current, and is electroplated on the second surfaces with a second average current. The second average current is 10 percent to 80 percent of the first average current.

Abstract: A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: An electronic device is provided. The electronic device includes a frame, a working panel, a case, and an adhesive material. The frame includes a side wall and a back plate. The working panel is disposed on the back plate. The case is disposed on the frame and adjacent to the working panel. The adhesive material is disposed on the case. The side wall has an outer surface facing away from the working panel. In a cross-section view of the electronic device, a portion of the adhesive material is in contact with the outer surface of the side wall of the frame, and a length of the adhesive material is greater than or equal to 50% of a length of the side wall of the frame along an extension direction.

Abstract: This application discloses electromagnetic energy mitigation assemblies and automotive vehicle components comprising the electromagnetic energy mitigation assemblies. An electromagnetic energy mitigation assembly includes a first electrically conductive layer and a second electrically conductive layer. First and second permalloy layers are along respective first and second opposite sides of the first electrically conductive layer. Third and fourth permalloy layers are along respective third and fourth opposite sides of the second electrically conductive layer. An electromagnetic noise suppression layer is sandwiched between the second and third permalloy layers. An automotive vehicle component includes an electromagnetic energy mitigation assembly configured to be positioned relative to one or more batteries of an automotive vehicle for providing electromagnetic shielding for the one or more batteries. The electromagnetic energy mitigation assembly includes a first electrically conductive layer.

Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

Abstract: A protection circuit including a voltage dividing circuit, a first comparator, a first switch, a second comparator, and a delay and logic circuit is provided. The voltage dividing circuit generates a first divided voltage and a second divided voltage based on a power voltage. The first comparator is configured to compare a reference voltage and the first divided voltage to generate a first comparison result. The second comparator is configured to compare the reference voltage and the second divided voltage to generate a second comparison result. The delay and logic circuit receives the first comparison result and the second comparison result. Wherein, according to a plurality of different states of the first comparison result and the second comparison result, the first switch is turned on to conduct part of current of the power voltage to a reference voltage terminal, or the first switch changes from turn-on to turn-off.

Abstract: A semiconductor device and a semiconductor package structure are provided. The semiconductor device includes a Radio Frequency (RF) circuit, at least one Ultra Thick Metal (UTM) layer and at least one aluminum (AP) mesh layer. The UTM layer is stacked on the RF circuit. The aluminum mesh layer is stacked on the UTM layer, and the UTM layer is connected to a power source or a ground through the aluminum mesh layer.

Abstract: In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.