Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

Abstract: A new class of multiplier cells (analog or digital) is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from first and second majority gates. The multiplier cell can also be implemented with a combination of two majority gates with majority and AND functions integrated in each of them. The two majority gates are coupled. Each of the first and second majority logic gates comprise a capacitor with non-linear polar material. The first and second majority gates receive the two inputs A and B that are to be multiplied. Other inputs received by the first and second majority gates are carry-in input, a sum-in input, and a bias voltage. The bias voltage is a negative voltage, which produces an integrated AND function in conjunction with a majority function. The second majority gate receives additional inputs, which are inverted output of the first majority gate.

Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Abstract: An antenna structure includes a loop radiation element and a first radiation element. The loop radiation element has a first end and a second end. A feeding point is positioned at the first end of the loop radiation element. A grounding point is positioned at the second end of the loop radiation element. The first radiation element has a first end and a second end. The first end of the first radiation element is coupled to a first connection point on the loop radiation element. The second end of the first radiation element is open. The antenna structure covers a first frequency band and a second frequency band.

Abstract: A computing environment can include a host system that maintains a guest system, and a hardware component configured to implement artificial intelligence (“AI”) methods of processing and analyzing date. The guest system can provide a virtual computing environment that receives a request to implement an AI application, and utilize a framework and a guest library to convert data from the AI application into an intermediate representation (“IR”). The host system can receive the IR with a virtual device (“VD”), and utilize an IR backend to translate the IR into hardware operations for the hardware component. Translated hardware operations can be provided to, and carried out by, the hardware component to provide an implementation of the AI application. Results of the hardware operations can be transmitted from the VD of the host system to a VD driver of the guest system, virtualizing the hardware component relative to the guest system.

Abstract: A network device serving as a head node on a first path may determine, based on obtained first constraint information, whether the first path meets a constraint condition of a target service, and further determine whether to switch a packet forwarding path from the first path to another path.

Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Abstract: A multicast data packet processing method performed by an intermediate node of a multicast tree includes: receiving a first Bit Index Explicit Replication (BIER) packet including a first label; obtaining, according to the first label, a second label corresponding to a multicast tree including the intermediate node; and obtaining a second BIER packet according to the second label and the first BIER packet, and sending the second BIER packet which includes the second label.

Abstract: An adder with first and second majority gates is provided. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Abstract: An antenna system includes a dielectric substrate, a ground plane, and a first antenna array. The ground plane is disposed on a second surface of the dielectric substrate. The first antenna array is disposed on a first surface of the dielectric substrate. The first antenna array includes a first transmission line, a first antenna element, a second antenna element, a third antenna element, a fourth antenna element, a fifth antenna element, and a sixth antenna element. The first transmission line has a first feeding point and is coupled to the first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, and the sixth antenna element. The first antenna element, the second antenna element, the third antenna element, the fourth antenna element, the fifth antenna element, and the sixth antenna element are all substantially arranged in a first straight line.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: A computing environment can include a host system that maintains a guest system, and a hardware component configured to implement artificial intelligence (“AI”) methods of processing and analyzing date. The guest system can provide a virtual computing environment that receives a request to implement an AI application, and utilize a framework and a guest library to convert data from the AI application into an intermediate representation (“IR”). The host system can receive the IR with a virtual device (“VD”), and utilize an IR backend to translate the IR into hardware operations for the hardware component. Translated hardware operations can be provided to, and carried out by, the hardware component to provide an implementation of the AI application. Results of the hardware operations can be transmitted from the VD of the host system to a VD driver of the guest system, virtualizing the hardware component relative to the guest system.

Abstract: An antenna module includes first and second antennas. The first antenna includes first, second and third radiators. A first end of the first antenna is a first feed-in end. The second and third radiators are connected to a second end of the first radiator. The second radiator has a first ground. The second antenna includes fourth, fifth and sixth radiators. The fifth radiator is connected to a second feed-in end of the fourth radiator. A second ground is located at an intersection between the fifth and sixth radiators. The antenna module covers first, second and third frequency bands.

Abstract: An antenna module includes first and second antennas. The first antenna includes first, second and third radiators. A first end of the first antenna is a first feed-in end. The second and third radiators are connected to a second end of the first radiator. The second radiator has a first ground. The second antenna includes fourth, fifth and sixth radiators. The fifth radiator is connected to a second feed-in end of the fourth radiator. A second ground is located at an intersection between the fifth and sixth radiators. The antenna module covers first, second and third frequency bands.

Abstract: A power turret device includes a turret set on which processing tools are disposed, a transmission gear set disposed in the turret set, an inner axle penetrating through the turret set, a clutch set disposed on the turret set and including first and second engagement units, and a driving set. The turret set includes a base and a turret portion having a head and a support shaft integrated with the head. The integration of the head and the support shaft facilitates the replacement of the turret portion and distributes the weight of the turret portion evenly to prevent undue wear. The turret portion rotates to move any selected processing tool to a proper processing position when the engagement units are separated. The engagement between the engagement units allows the selected processing tool to rotate on its axis. The processing accuracy is increased and the service life is prolonged.

Abstract: A multicast data packet processing method in a point-to-multipoint (P2MP)-based bit index explicit replication (BIER) multicast tree, which includes an intermediate node configured to use P2MP to forward a BIER packet, includes receiving a first multicast data packet with a BIER header having a first label. The method further includes obtaining a first forwarding entry based on the first label. The first forwarding entry includes the first label, a first identifier identifying the multicast tree, and a second identifier instructing to perform P2MP forwarding. The method further includes obtaining, based on the first identifier, a second forwarding entry including the first identifier and a second label. The method further includes obtaining a second multicast data packet based on the second identifier, the second forwarding entry, and the first multicast data packet, and sending the second multicast data packet. The second multicast data packet includes the second label.

Abstract: A packet loss processing method and a network device are provided. The method includes: A first node obtains a first forwarding label of a first packet, where the first packet is a discarded packet. The first node determines, based on the first forwarding label, that the first node does not have a LSP corresponding to the first forwarding label. The first node sends a first message to a second node, where the first message includes the first forwarding label, and the first message is used to indicate that the first node does not have the LSP corresponding to the first forwarding label. The second node may be, for example, a peer node of the first node. The first node sends the message to the peer node, to indicate that the first node does not have the LSP corresponding to the forwarding label.