Abstract: A vacuum switching valve and a suction system having the same. The vacuum switching valve comprises: a valve body, comprising a first end and a second end, the second end being provided with an air inlet, an air outlet and a through hole; a valve element movably arranged in the valve body; a cylinder, the cylinder being connected to the first end and the valve element, the cylinder drives the valve element to move in the valve body, to close or open the air inlet; a stopper passing through the through hole, the stopper comprising a third end and a fourth end, the third end being connected to the valve element, the fourth end being located on the side of the through hole away from the valve element.

Abstract: A case with screw thread in a sealed manner for communication equipment includes an upper cover and a bottom cover. The inner surface of the upper cover has an internal screw thread. The outer surface of the bottom cover has an external screw thread. When the external screw thread is fixed with the internal screw thread, the inner surface of the upper cover is in contact with the outer surface of the bottom cover in a sealed state, and the upper cover and the bottom cover form a receiving space. The case provides the following advantages: quickly and repeated assembly and disassembly; no need for any space for bolts so as to minimizes the size; without bolt, no need for washers or sealant; good sealing properties and good waterproof effect so as to prevent water from entering the case.

Abstract: A circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor has a first end and a second end. The second transistor has a first end and a second end, wherein the first end of the second transistor is coupled to the first end of the first transistor. The third transistor has a first end and a second end, wherein the second end of the third transistor is coupled to the second end of the second transistor. The fourth transistor has a first end coupled to the second end of the first transistor. The fourth transistor has a bottom gate and an oxide semiconductor layer, and the second transistor has a top gate and a silicon semiconductor layer.

Abstract: AB STRACT An imaging lens system for tracking a celestial body includes, sequentially in a direction from the object side to the image side: a first lens group including, sequentially in the foregoing direction, either a negative-dioptric-power and two positive-dioptric-power lens elements, or a positive-dioptric-power, a negative-dioptric-power, and another positive-dioptric-power lens element; a second lens group including two negative-dioptric-power lens elements; and a third lens group including, sequentially in the foregoing direction, either a positive-dioptric-power, a negative-dioptric-power, and another positive-dioptric-power lens element, or two positive-dioptric-power, a negative-dioptric-power, and another positive-dioptric-power lens element. An aperture stop is located at the center of the imaging lens system symmetrically, allowing marginal rays to pass through the center of each lens element. The positive- and negative-dioptric-power lens elements contribute to a balanced field curvature.

Abstract: The present disclosure provides a bispecific antibody including a binding domain that binds to CD112R and a binding domain that binds to TIGIT, and the binding domain that binds to CD112R includes: HCDR1, HCDR2 and HCDR3 of the amino acid sequence set forth in SEQ ID NO: 1, and/or LCDR1, LCDR2 and LCDR3 of the amino acid sequence set forth in SEQ ID NO: 2; and the HCDR1, HCDR2, HCDR3, LCDR1, LCDR2 and LCDR3 are defined according to the Kabat, IMGT, Chothia, AbM or Contact numbering system. The present disclosure further provides a polynucleotide encoding the antibody, an expression vector, a host cell and a method for expressing and purifying the antibody, a pharmaceutical composition including the antibody of the present disclosure, and use of the bispecific antibody for treating cancer.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: Some embodiments of the present disclosure provide an N-type TOPCon cell with double-sided aluminum paste electrodes, and a preparation method therefor. The front side of the cell is provided with a front-side silver main grid and a front-side aluminum fine grid, and the back side is provided with a back-side silver main grid and a back-side aluminum fine grid. The method for preparing the cell includes: texturing?B diffusion?BSG removal?alkali polishing?depositing a tunnel oxide layer and a polysilicon layer on a back side of a substrate by means of LPCVD?P diffusion on the back side?PSG removal?plating removal?deposition of an AlOx preparatory layer and a first SiNxHy preparatory layer on the front side?deposition of a second preparatory layer SiNxHy on the back side?UV laser ablation on the front side of the substrate and the back side of the substrate?screen printing.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. The semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. The electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally couped to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes: at least one gate structure having a first side and a second side opposite to each other; a first source/drain (S/D) feature disposed at the first side of the at least one gate structure; a second S/D feature disposed at the second side of the at least one gate structure; a first metal-to-drain/source (MD) contact disposed on the first S/D feature; and a second MD contact disposed on the second S/D feature, wherein a contact area between the first MD contact and the first S/D feature is greater than a contact area between the second MD contact and the second S/D feature.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A tool box is provided, including: a main body, including an intermediate member and two shell members, the intermediate member including a first connection portion and a second connection portion, the first connection portion and the second connection portion being arranged in a first direction, one of the two shell members being rotatably connected to the first connection portion, the other of the two shell members being rotatably connected to the second connection portion so that the two shell members are capable of covering two sides of the intermediate member in the first direction; a buckle member, movably disposed on the main body and configured to restrict the two shell members from rotating relative to the intermediate member.