Patents by Inventor Sheng Feng

Sheng Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250246113
    Abstract: An electronic device includes a first transistor, a second transistor, a plurality of driver units, and an electronic unit. The first transistor includes a first control end. The second transistor is coupled to the first transistor and includes a second control end for receiving a pulse signal. The pulse signal has a pulse width. The driver units are coupled in parallel. Each driver unit includes an input end coupled to the first control end, an output end coupled to a node, and a control end for receiving an enable signal. The electronic unit is coupled to the node. The driver units provide currents to the electronic unit according to received enable signals. A current flowing through the electronic unit is modulated according to the pulse width of the pulse signal.
    Type: Application
    Filed: December 26, 2024
    Publication date: July 31, 2025
    Applicant: InnoLux Corporation
    Inventors: Yu-Shen TSAI, Cheng-Hsiao LIN, Sheng-Feng HUANG
  • Publication number: 20250241275
    Abstract: An intelligent pet oral cleaning water dispenser comprises a water tank; a detachable water storage area and a host machine are arranged on the water tank; a water leakage port is arranged on the detachable water storage area; a filter screen is arranged below the water leakage port; a diverted and distributed water pipe is arranged on the uppermost part of the host machine; the bottom of the diverted and distributed water pipe is connected to a water outlet; a water inlet is arranged next to the water outlet; a reaction tank is arranged below the water inlet and the water outlet; a micropump is arranged below the reaction tank; a circuit board is arranged next to the micropump; a switch and a charging port are arranged on the circuit board; a battery is arranged below the micropump.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 31, 2025
    Inventors: Qiang Dai, Sheng Feng, Kai Wei
  • Patent number: 12354997
    Abstract: A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiang Chiu, Chia-Min Lin, Tzu-Ting Chou, Sheng-Feng Weng, Chao-wei Li, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 12354929
    Abstract: A package structure including a semiconductor die, an encapsulant, a redistribution structure, and a through insulating via is provided. The first redistribution structure includes an insulating layer and a circuit layer. The semiconductor die is disposed on the first redistribution structure. The semiconductor die includes a semiconductor base, through semiconductor vias, a dielectric layer, and bonding connectors. Through semiconductor vias penetrate through the semiconductor base. The dielectric layer is disposed on a backside of the semiconductor base. The dielectric layer of the semiconductor die is bonded with the insulating layer of the first redistribution structure. The bonding connectors are embedded in the dielectric layer and connected to the through semiconductor vias. The bonding connectors of the semiconductor die are bonded with bonding pads of the circuit layer. The encapsulant is disposed on the first redistribution structure and encapsulates the semiconductor die.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Sheng-Feng Weng, Ming-Yu Yen, Wei-Jhan Tsai, Chao-Wei Chiu, Chao-Wei Li, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20250218938
    Abstract: A device including: a first active region; first and second ohmic-contact layers correspondingly on, and coupled to, a front side and a back side of a first portion of the first active region; a metal-to-source/drain (MD) contact including a first part on the first ohmic-contact layer and at least a second part or a third part correspondingly aside a first lateral side or a second lateral side of the first portion of the first active region, the first part of the MD contact being coupled to the first ohmic-contact layer; and a buried-via (BV) structure including: a first part under, and coupled to, the second ohmic-contact layer; and a second part under, and coupled to, the MD contact.
    Type: Application
    Filed: April 29, 2024
    Publication date: July 3, 2025
    Inventors: Wei-Cheng KANG, Sheng-Feng HUANG, Shang-Wei FANG, Meng-Hung SHEN, Jiann-Tyng TZENG
  • Patent number: 12334424
    Abstract: A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Wei-Jhan Tsai, Sheng-Feng Weng, Ching-Yao Lin, Ming-Yu Yen, Kai-Fung Chang, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20250167060
    Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
    Type: Application
    Filed: January 23, 2025
    Publication date: May 22, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Min Lin, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Sheng-Feng Weng, Yao-Tong Lai
  • Publication number: 20250148953
    Abstract: An electronic device includes a substrate, at least a data line disposed on the substrate for transmitting data, and at least a pixel circuit disposed on the substrate. The pixel circuit includes a memory element, a capacitor, a first switch element, a second switch element, and a third switch element. The capacitor is electrically connected to the memory element. One end of the first switch element is electrically connected to the data line. The second switch element is electrically connected between the first switch element and the memory element. The third switch element is electrically connected between the first switch element and the capacitor. When the second switch element is turned on, the data is transmitted to the memory element. When the third switch element is turned on, the data is transmitted to one end of the capacitor.
    Type: Application
    Filed: October 9, 2024
    Publication date: May 8, 2025
    Inventors: Cheng-Min WU, Sheng-Feng HUANG
  • Publication number: 20250148999
    Abstract: An electronic device includes a substrate, a first transistor, a second transistor, an electronic unit and a conductor. The first transistor is disposed on the substrate and comprises a first semiconductor layer. The second transistor is disposed on the substrate and comprises a second semiconductor layer, wherein a material of the first semiconductor layer is different from a material of the second semiconductor layer. The electronic unit is disposed on the substrate and electrically connected to the second transistor. The conductor is electrically connected to the first semiconductor layer and the second semiconductor layer.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Sheng-Feng HUANG, Chien-Feng SHIH
  • Publication number: 20250131894
    Abstract: A circuit includes a first switching element, a second switching element, a third switching element and a fourth switching element. The first switching element has a first end and a second end. The second switching element has a first end and a second end, wherein the first end of the second switching element is coupled to the first end of the first switching element. The third switching element has a first end and a second end, wherein the second end of the third switching element is coupled to the second end of the second switching element. The fourth switching element has a first end coupled to the second end of the first switching element. The fourth switching element has a bottom gate and the second switching element has a top gate.
    Type: Application
    Filed: December 26, 2024
    Publication date: April 24, 2025
    Inventors: Sheng-Feng HUANG, Akihiro IWATSU, Cheng-Min WU, Kuanfeng LEE
  • Publication number: 20250132268
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 24, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 12283735
    Abstract: A gapless ferrite structure for circulator or isolator includes a first base having a first flange and a first limit slot surrounded by the first flange, a second base having a second flange and a second limit slot surrounded by the second flange, a ferrite with two ends accommodated in the first limit slot and the second limit slot respectively, two limit magnets installed on the first base and the second base respectively and configured to be corresponsive to the ferrite to generate an attraction force on the ferrite, and two sealing units configured between an end of the ferrite and the first limit slot and between the other end of the ferrite and the second limit slot respectively. In this way, a gapless structure can be formed on a signal transmission path in a circulator or isolator.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: April 22, 2025
    Assignee: Universal Microwave Technology, Inc.
    Inventors: Tung-Yi Wu, Sheng-Feng Yeh, Wun-Kai Wu, Sung-Fan Liu, Chien-Chih Lee, Jen-Ti Peng
  • Patent number: 12279535
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: April 15, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Ya-Sheng Feng
  • Publication number: 20250105782
    Abstract: A solar power system is provided. The solar power system includes a first solar photovoltaic panel and a first DC optimizer. The first solar photovoltaic panel converts light energy into electrical energy to generate a first solar voltage. The first DC optimizer receives the first solar voltage and performs a first voltage decreasing operation on the first solar voltage according to a first pulse width modulation signal to generate a first conversion voltage. The first DC optimizer adjusts a first duty cycle of the first pulse width modulation signal according to the first conversion voltage.
    Type: Application
    Filed: December 14, 2023
    Publication date: March 27, 2025
    Inventor: Sheng-Feng CHEN
  • Publication number: 20250078770
    Abstract: An electronic device includes a substrate, a first transistor, a second transistor, an electronic unit and a conductor. The first transistor is disposed on the substrate and comprises an oxide semiconductor layer. The second transistor is disposed on the substrate and comprises a silicon semiconductor layer. The electronic unit is disposed on the substrate and electrically connected to the second transistor. The conductor is electrically connected to the oxide semiconductor layer and the silicon semiconductor layer.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: Sheng-Feng HUANG, Chien-Feng SHIH
  • Publication number: 20250069434
    Abstract: A device for processing human face image data includes an extractor arranged to receive image data and to extract therefrom a set of features, and two or more classifiers arranged to receive a set of features from the extractor and to return a value for classifying or labelling the corresponding image data. The extractor is a deep neural network and the two or more classifiers comprise a single common neural network and one or more neural networks specific to subsets of human face images. The classifiers are trained specifically to detect particular subsets of human face images.
    Type: Application
    Filed: December 23, 2022
    Publication date: February 27, 2025
    Applicant: UNISSEY
    Inventor: Sheng FENG
  • Patent number: 12230549
    Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Min Lin, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Sheng-Feng Weng, Yao-Tong Lai
  • Patent number: 12218082
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 12205667
    Abstract: The present invention provides a multi-die package including main die, a memory die, a first set of pins and a second set of pins. The main die includes a memory controller, a first set of pads, a second set of pads and a third set of pads. The memory die is coupled to the first set of pads and the second set of pads of the main die. The first set of pins is coupled to the third set of pads of the main die. The second set of pins is coupled to the second set of pads of the main die. The memory controller accesses the memory die through the first set of pads and the second set of pads, and the memory controller accesses a memory chip external to the multi-die package through the second set of pads and the third set of pads.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 21, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventor: Sheng-Feng Chung
  • Publication number: 20250021735
    Abstract: A semiconductor device includes: an area formed on a substrate and organized into a plurality of cell rows extending along a first direction; a first cell disposed across a first one of the plurality of cell rows, the first cell having a first height along a second direction perpendicular to the first direction; and a second cell disposed across a second one and half of a third one of the plurality of cell rows, the second cell having a second height. The first cell essentially consists of a first active region with a first conductivity and a second active region with a second conductivity. The second cell essentially consists of a third active region with the first conductivity and a fourth active region with the second conductivity. The second height is 1.5 times as high as the first height.
    Type: Application
    Filed: July 12, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Wei Fang, Jiann-Tyng Tzeng, Sheng-Feng Huang