Abstract: The invention relates to a multimedia system and a multimedia operation method. The multimedia system includes a first portable electronic device, a collaboration device, a camera, and an audio-visual processing device. The first portable electronic device provides a first operation instruction. The collaboration device is coupled to the first portable electronic device and receives the first operation instruction. The collaboration device provides a multimedia picture, and the multimedia picture is changed with the first operation instruction. The camera provides a video image. The audio-visual processing device is coupled to the collaboration device and the camera, and the audio-visual processing device receives the multimedia picture and a video image, and outputs a synthesized image with an immersive audio-visual effect according to the multimedia picture and the video image.

Abstract: The present invention discloses a new dual polarized array waveguide antenna configured above a signal processing substrate and sequentially including an antenna array substrate, a coupling substrate and a waveguide body. The antenna array substrate includes a plurality of patches, each of which having a first coupling portion and a second coupling portion coupled to the signal processing substrate. The top surface of the coupling substrate includes a plurality of coupling pads corresponding to the patches, and each coupling pad is configured above an intersection area of the first coupling portion and the second coupling portion. The waveguide body includes a plurality of waveguide channels passing through the waveguide body and corresponding to the coupling pads. Each waveguide channel has a first ridge pair and a second ridge pair projecting from wall surfaces.

Abstract: A catadioptric optical system in sequence of ray tracing comprises a first mirrors group of Ritchey-Chrétien type hyperbolic mirrors with positive diopter including a concave primary mirror having a central through hole and a convex secondary mirror, a second corrector lens group with negative diopter positioned at the image-side of the first mirrors group including a first meniscus lens element having positive refractive power and a convex object-side surface, a second lens element having negative refractive power and biconcave surfaces, a third meniscus lens element having negative refractive power and a concave object-side surface, and a fourth lens element having positive refractive power and biconvex surfaces. The infinite conjugate beams of incident light within field of view pass through the catadioptric optical system to become a corrected beam having a small CRA angle.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: The present invention relates to method of treating HBV infection in a human patient, wherein the method comprises administration of a therapeutically effective amount of Compound (I), or a pharmaceutically acceptable salt thereof.

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.

Abstract: The disclosure provides an electronic device. The electronic device includes a pixel array and a first driving circuit. The pixel array is disposed on a substrate and includes a plurality of sub-pixel rows. The first driving circuit is disposed on the substrate and located on one side of the pixel array. The first driving circuit includes a plurality of demultiplexer circuits and a plurality of switching circuits. The demultiplexer circuits include a first demultiplexer circuit. The switching circuits include a first switching circuit. The first switching circuit is coupled to the first demultiplexer circuit, and the first demultiplexer circuit is coupled to at least three of the plurality of sub-pixel rows.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Abstract: An image capturing apparatus and an electronic device are provided. The image capturing apparatus includes: a light-transmitting cover plate, a light source component, a sensor component, and a lens disposed between the light source component and the sensor component. A preset angle is formed between a central axis of the lens and a normal of the light source component. A light generated by the light source component is transmitted through the light-transmitting cover plate, and then is scattered by the object to be captured, and the scattered light is focused by the lens to the sensor component. The light source component is disposed outside of a depth of field of the lens, and the object to be captured is disposed within the depth of field of the lens.

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: A chip package module is provided. The chip package module includes a package substrate, a chip, and a conductive connector assembly. The chip having a first surface and a second surface opposite thereto is disposed on the package substrate. The first surface is divided into a first region, a second region, and a third region, and the second region is located between the first and third regions. The chip includes a flip-chip pad group disposed in the first region, a wire-bonding pad group disposed in the third region, and a signal pad group disposed in the second region. The conductive connector assembly is electrically connected between the chip and the package substrate. One of the flip-chip pad group and the wire-bonding pad group is electrically and physically connected to the conductive connector assembly, and the other one is not physically connected to the conductive connector assembly.

Abstract: The present invention discloses a new single polarized array waveguide antenna adapted to be configured above a signal processing substrate, and including an antenna array substrate and a waveguide body. The antenna array substrate includes a plurality of antenna units, each of which having a coupling portion and an impedance matching portion. The waveguide body is configured above the antenna array substrate, and includes a plurality of waveguide channels passing through the waveguide body. Each waveguide channel has a first ridge and a second ridge projecting from wall surfaces and arranged opposite to each other. The first ridge has a first lower withdrawn edge on a lower section of the waveguide channel, and the second ridge has a second lower withdrawn edge on the lower section of the waveguide channel.

Abstract: Provided is an expression vector including a nucleotide sequence for encoding lysine decarboxylase CadA, and a sequence of a constitutive promoter for regulating the expression of the nucleotide sequence. Also provided is a recombinant microorganism including the expression vector and a method of producing 1,5-diaminopentane by using the recombinant microorganism.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: A valve comprising housing body, partition plate, and collecting device. The housing body defines a housing cavity. The partition plate is provided in the housing cavity. A leakage passage extends along the partition plate through the housing body. The collecting device comprises a lower piece, an upper piece, and a connector connecting them. The upper piece and the lower piece cover a leakage passage upper port and a leakage passage lower port, respectively. The lower piece comprises a collecting cavity communicating with the leakage passage lower port. The lower piece and lower part of the housing body are provided with lower fitting assembly. The upper piece and upper part of the housing body are provided with an upper fitting assembly. The lower piece and the upper piece are fitted on the housing body in place by means of the lower fitting assembly, the upper fitting assembly and the connector.

Abstract: The present invention discloses a new dual polarized array waveguide antenna configured above a signal processing substrate and sequentially including an antenna array substrate, a coupling substrate and a waveguide body. The antenna array substrate includes a plurality of patches, each of which having a first coupling portion and a second coupling portion coupled to the signal processing substrate. The top surface of the coupling substrate includes a plurality of coupling pads corresponding to the patches, and each coupling pad is configured above an intersection area of the first coupling portion and the second coupling portion. The waveguide body includes a plurality of waveguide channels passing through the waveguide body and corresponding to the coupling pads. Each waveguide channel has a first ridge pair and a second ridge pair projecting from wall surfaces.