Patents by Inventor Sheng-Hsiung Chen

Sheng-Hsiung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384344
    Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
  • Publication number: 20220382958
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • Publication number: 20220367358
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 11501052
    Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
  • Publication number: 20220358277
    Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
  • Patent number: 11495619
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20220335199
    Abstract: A semiconductor device including a cell region which includes components representing a circuit arranged such that a rectangular virtual perimeter is drawable around substantially all of the components and includes first and second virtual side boundaries, the components including: a first conductor which is an intra-cell conductor of a first signal that is internal to the circuit, a first end of the intra-cell conductor being substantially a minimum virtual boundary offset inside the first virtual side boundary; and a second conductor of a second signal of the circuit; a portion of the second conductor having a first end which extends outside the first virtual side boundary by a protrusion length substantially greater than the minimum virtual boundary offset; and a second end of the second conductor being receded inside the second virtual side boundary by a first gap substantially greater than the minimum virtual boundary offset.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Sheng-Hsiung CHEN, Po-Hsiang HUANG
  • Publication number: 20220335194
    Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Limited
    Inventors: Sheng-Hsiung Chen, Jerry Kao, Kuo-Nan Yang, Jack Liu
  • Publication number: 20220320018
    Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Fong-yuan CHANG, Cheng-Hung YEH, Hsiang-Ho CHANG, Po-Hsiang HUANG, Chin-Her CHIEN, Sheng-Hsiung CHEN, Aftab Alam KHAN, Keh-Jeng CHANG, Chin-Chou LIU, Yi-Kan CHENG
  • Patent number: 11449656
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
  • Patent number: 11437319
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 11423204
    Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
  • Patent number: 11397842
    Abstract: A method (of generating a layout diagram) includes: generating a shell including wiring patterns in a first layer of metallization, the wiring patterns having long axes which are substantially aligned with corresponding tracks that extend in a first direction, the wiring patterns having a default arrangement which has, relative to the corresponding tracks, a first amount of free space; and refining the shell into a cell, the refining including selectively shrinking, in the first direction, one or more of the wiring patterns resulting in a second amount of free space, the second amount being greater than the first amount, increasing, in the first direction, one or more chosen ones of the wiring patterns (chosen patterns), and backfilling the second amount of free space with one or more of at least one dummy pattern or at least one wiring pattern.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Sheng-Hsiung Chen, Po-Hsiang Huang
  • Patent number: 11394886
    Abstract: An electronic device and a control method for an image capture device thereof are provided. The control method includes: setting an initial visual field; tracking an object in the initial visual field to obtain a first reference position; obtaining a reference visual field according to the first reference position; generating visual field adjusting information according to the initial visual field and the reference visual field; and adjusting, based on the visual field adjusting information, the reference visual field to obtain a target visual field according to a size of the object, where an area ratio between an area of the object and an area of the target visual field is larger than a ratio threshold, and the area ratio is smaller than 1.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: July 19, 2022
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Kuan-Yuan Chen, Sheng-Hsiung Chang, Chun-Hsiang Chang
  • Patent number: 11387839
    Abstract: A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: July 12, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Sheng-Yen Shih, Shih-Hsiung Huang, Yu-Chang Chen
  • Publication number: 20220214712
    Abstract: A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Jerry Chang Jui KAO, Huang-Yu CHEN, Sheng-Hsiung CHEN, Jack LIU, Yung-Chen CHIEN, Wei-Hsiang MA, Chung-Hsing WANG
  • Publication number: 20220198122
    Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Hung-Chih OU, Chun-Yao KU, Shao-Huan WANG
  • Patent number: 11367695
    Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-yuan Chang, Cheng-Hung Yeh, Hsiang-Ho Chang, Po-Hsiang Huang, Chin-Her Chien, Sheng-Hsiung Chen, Aftab Alam Khan, Keh-Jeng Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 11281836
    Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Ho Che Yu, Lee-Chung Lu, Ni-Wan Fan, Po-Hsiang Huang, Chi-Yu Lu, Jeo-Yen Lee
  • Patent number: 11275886
    Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Yao Ku, Shao-Huan Wang, Hung-Chih Ou