Patents by Inventor Sheng-Hsiung Chen

Sheng-Hsiung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11449656
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
  • Patent number: 11437319
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 11423204
    Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Hsiung Chen, Jerry Chang Jui Kao, Kuo-Nan Yang, Jack Liu
  • Patent number: 11397842
    Abstract: A method (of generating a layout diagram) includes: generating a shell including wiring patterns in a first layer of metallization, the wiring patterns having long axes which are substantially aligned with corresponding tracks that extend in a first direction, the wiring patterns having a default arrangement which has, relative to the corresponding tracks, a first amount of free space; and refining the shell into a cell, the refining including selectively shrinking, in the first direction, one or more of the wiring patterns resulting in a second amount of free space, the second amount being greater than the first amount, increasing, in the first direction, one or more chosen ones of the wiring patterns (chosen patterns), and backfilling the second amount of free space with one or more of at least one dummy pattern or at least one wiring pattern.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Sheng-Hsiung Chen, Po-Hsiang Huang
  • Publication number: 20220214712
    Abstract: A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Jerry Chang Jui KAO, Huang-Yu CHEN, Sheng-Hsiung CHEN, Jack LIU, Yung-Chen CHIEN, Wei-Hsiang MA, Chung-Hsing WANG
  • Publication number: 20220198122
    Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Hung-Chih OU, Chun-Yao KU, Shao-Huan WANG
  • Patent number: 11367695
    Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-yuan Chang, Cheng-Hung Yeh, Hsiang-Ho Chang, Po-Hsiang Huang, Chin-Her Chien, Sheng-Hsiung Chen, Aftab Alam Khan, Keh-Jeng Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 11281836
    Abstract: A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Ho Che Yu, Lee-Chung Lu, Ni-Wan Fan, Po-Hsiang Huang, Chi-Yu Lu, Jeo-Yen Lee
  • Patent number: 11275886
    Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Yao Ku, Shao-Huan Wang, Hung-Chih Ou
  • Publication number: 20220067266
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
  • Publication number: 20220058330
    Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Lid.
    Inventors: Sheng-Hsiung CHEN, Chung-Te LIN, Fong-Yuan CHANG, Ho Che YU, Li-Chun TIEN
  • Publication number: 20220035982
    Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Inventors: CHIN-SHEN LIN, WAN-YU LO, SHAO-HUAN WANG, KUO-NAN YANG, CHUNG-HSING WANG, SHENG-HSIUNG CHEN, HUANG-YU CHEN
  • Patent number: 11182533
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 23, 2021
    Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 11170152
    Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien
  • Patent number: 11170149
    Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang
  • Publication number: 20210342514
    Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 4, 2021
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Publication number: 20210326510
    Abstract: A method (of generating a layout diagram) includes identifying, in the layout diagram, a group of three or more cells arranged so as to exhibit two or more edge-pairs (EPs) that are edge-wise abutted relative to a first direction. The method further includes, for each of at least one but fewer than all of the three or more cells, selectively moving a given one of cells corresponding to one of the members of the corresponding EP resulting in at least a minimum gap in the first direction between the members of the corresponding EP.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Inventors: Meng-Kai HSU, Sheng-Hsiung CHEN, Wai-Kei MAK, Ting-Chi WANG, Yu-Hsiang CHENG, Ding-Wei HUANG
  • Patent number: 11138362
    Abstract: A method of updating a boundary space configuration of an IC layout cell includes identifying a pin in the IC layout cell as a boundary pin, determining that a boundary spacing of the boundary pin is capable of being increased, and based on the determination that the boundary spacing of the boundary pin is capable of being increased, modifying the IC layout cell by increasing the boundary spacing of the boundary pin. At least one of the identifying, determining, or modifying is executed by a processor of a computer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Sheng-Hsiung Chen, Fong-Yuan Chang
  • Patent number: 11138360
    Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Hui-Zhong Zhuang, Meng-Hsueh Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 11132488
    Abstract: A method of modifying a cell includes determining a number of pins in a maximum overlapped pin group region. The method further includes determining a number of routing tracks within a span region of the maximum overlapped pin group region. The method further includes comparing the number of pins and the number of routing tracks within the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang