Abstract: In an embodiment, a three-dimensional integrated circuit (3DIC) package includes an interposer, a plurality of connection pads, a plurality of dummy patterns, a plurality of integrated circuit structures and an underfill layer. The connection pads are disposed on and electrically connected to a first side of the interposer. The dummy patterns are disposed on the first side of the interposer and around the plurality of connection pads. The integrated circuit structures are electrically connected to the connection pads through a plurality of first bumps. The underfill layer surrounds the first bumps and covers the dummy patterns.

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

Abstract: The present invention discloses a ?-transaminase mutant obtained through DNA synthetic shuffling combined mutation. The ?-transaminase mutant is obtained through point mutation of a wild type ?-transaminase from Aspergillus terrus. The amino acid sequence of the wild type ?-transaminase is shown in SEQ ID NO: 1. The mutation site of the ?-transaminase mutant is any one of: (1) F115L-H210N-M150C-M280C; (2) F115L-H210N; (3) F115L-H210N-E253A-I295V; (4) I77L-F115L-E133A-H210N-N245D; (5) I77L-Q97E-F115L-L118T-E253A-G292D; (6) I77L-E133A-N245D-G292D; and (7) H210N-N245D-E253A-G292D. According to the present invention, forward mutations obtained in the previous stage are randomly combined through a DNA synthetic shuffling combined mutation method.

Abstract: A method of fabricating a memory device includes forming a plurality of first nanostructures, a plurality of second nanostructures, a plurality of third nanostructures, and a plurality of fourth nanostructures; separating the plurality of first nanostructures and the plurality of second nanostructures with a dielectric fin structure; forming a first gate structure wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure; forming a second gate structure wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure; and forming a first interconnect structure coupled to one of the first gate structure or second gate structure. The dielectric structure also extends along the first lateral direction. The first and second gate structures extend along a second lateral direction perpendicular to the first lateral direction.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The first heat conductive structure has a first corner portion and a first protruding portion connected to the first corner portion, and the first protruding portion passes through the ring dam. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.

Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.

Abstract: Disclosed in the present invention are a thiophene ring compound, a preparation method therefor and an application thereof. The structure of the thiophene ring compound of the present invention is as shown in formula I. The compound of the present invention has good affinity and agonistic activity against at least one of a dopamine receptor and a 5-hydroxytryptamine receptor.

Abstract: Embodiments of the present application provide a rotor and a motor. The rotor has a plurality of through-hole groups. Each through-hole group has a plurality of through-holes distributed in a radial direction. The rotor also has auxiliary holes. Each auxiliary hole is located between every two radially adjacent through-holes. A sectional area of each auxiliary hole is less than a sectional area of each through-hole. When a first angle, a second angle and a third angle are defined between three portions of each auxiliary hole and the q-axis respectively, the third angle is greater than or equal to the first angle, and the third angle is less than or equal to the second angle.

Abstract: A computing system includes one or more electronic components, a first programmable device, and a baseboard management controller (BMC). The first programmable device is communicatively coupled to a first subset of the one or more electronic components. The first programmable device is configured to detect event activities associated with the first subset and to store the event activities as stored first event data. The BMC includes a system event log. The BMC is communicatively coupled to the first programmable device. The BMC is configured to receive the stored first event data and to write the stored first event data in the system event log.

Abstract: In an embodiment, a three-dimensional integrated circuit (3DIC) package includes an interposer, a plurality of connection pads, a plurality of dummy patterns, a plurality of integrated circuit structures and an underfill layer. The connection pads are disposed on and electrically connected to a first side of the interposer. The dummy patterns are disposed on the first side of the interposer and around the plurality of connection pads. The integrated circuit structures are electrically connected to the connection pads through a plurality of first bumps. The underfill layer surrounds the first bumps and covers the dummy patterns.

Abstract: A cockpit display system includes a cockpit, a first display apparatus, a second display apparatus, a first light sensor, a second light sensor and a brightness distribution calculation module. The first light sensor is suitable for detecting a first ambient light brightness. The second light sensor is suitable for detecting a second ambient light brightness. The brightness distribution calculation module is suitable for respectively calculating a first brightness, a second brightness, a third brightness and a fourth brightness of the first display area and the second display area of the first display apparatus and the third display area and the fourth display area of the second display apparatus under a same display gray level according to the first ambient light brightness and the second ambient light brightness. The first brightness, the second brightness, the third brightness and the fourth brightness are different from each other.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer and a first dielectric layer disposed on the first metal layer. A range of a difference between a coefficient of thermal expansion of the first dielectric layer and a coefficient of thermal expansion of the first metal layer is 0% to 70% of the coefficient of thermal expansion of the first dielectric layer.

Abstract: Embodiments of the application provide a display panel, a display screen and a display device. The display panel includes a backplane, a color filter layer, and a black matrix between the backplane and the color filter layer. The backplane includes a base substrate, the color filter layer includes a plurality of sub-pixel color filters, and the plurality of sub-pixel color filters are arranged along a plane of the color filter layer and spliced together to form the color filter layer.

Abstract: An electronic device may include a display and an optical sensor formed underneath the display. The electronic device may include a plurality of transparent windows that overlap the optical sensor. The resolution of the display panel may be reduced in some areas due to the presence of the transparent windows. To prevent a visible border between the reduced resolution areas of the display and full resolution areas of the display, uniformity compensation circuitry may be used to compensate pixel data. The uniformity compensation circuitry may output compensated pixel data for the display using one or more compensation maps that include compensation factors associated with pixel locations. The uniformity compensation circuitry may also use region-specific gamma look-up tables to apply different gamma curves to pixels in different regions of the display. The uniformity compensation circuitry may also be used to form a transition region between different regions of the display.

Abstract: A method of adaptively controlling a brushless DC motor includes steps of: controlling the brushless DC motor rotating at a first speed according to an operation curve, accumulating a running time of the brushless DC motor, estimating a remaining used time of a bearing of the brushless DC motor according to the accumulated running time, executing an alarm operation when the remaining used time is less than a predetermined time, and decreasing the speed of the brushless DC motor to run at a second speed to prolong the used time of the bearing.

Abstract: A signal quality optimization system and a signal quality optimization method are provided.

Abstract: An expansion card frame assembly is configured to support a riser card and an expansion card. The expansion card frame assembly includes a frame, a pivotable component and a stopper. The frame is configured to support the riser card, and the expansion card is configured to be inserted into the riser card. The pivotable component is pivotably disposed on the frame and configured to be located aside the expansion card. The stopper is movably disposed on the pivotable component and configured to be located at one side of the expansion card which is located farther away from the riser card.

Abstract: A co-packaged structure for optics and electrics includes a substrate, an optical module and an electrical connection layer. The optical module includes a carrier and an optical transceiver unit. The carrier is mounted on the substrate. The optical module is mounted on the carrier. The electrical connection layer is mounted on the substrate, and the carrier is electrically connected with a circuitry on the substrate through the electrical connection layer. A plurality of fiber accommodation through hole are formed on the substrate and correspond to the optical transceiver unit.

Abstract: A package assembly includes an interposer module on a package substrate, a liquid alloy thermal interface material (TIM) on the interposer module, a seal ring surrounding the liquid alloy TIM, and a package lid on the liquid alloy TIM and seal ring, wherein the seal ring, interposer module and package lid seal the liquid alloy TIM.