Patents by Inventor Sheng Wang
Sheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250081650Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer over the substrate, a first photodiode and a second photodiode in the first epitaxial layer, and a trench isolation structure between the first photodiode and the second photodiode. The first photodiode includes a first doped region having a first conductivity type. The first photodiode includes a second doped region, overlying the first doped region, having a second conductivity type different than the first conductivity type. The first photodiode includes a third doped region, overlying the first doped region, having the second conductivity type. A first distance between a sidewall of the third doped region and an uppermost surface of the first epitaxial layer is between about a hundredth to about a fifth of a second distance between a sidewall of the trench isolation structure and the uppermost surface of the first epitaxial layer.Type: ApplicationFiled: August 28, 2023Publication date: March 6, 2025Inventors: Wen-Sheng WANG, Yi-Hsuan Fan, Yen-Ting Chen
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Publication number: 20250081730Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.Type: ApplicationFiled: June 26, 2024Publication date: March 6, 2025Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
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Publication number: 20250081622Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.Type: ApplicationFiled: December 6, 2023Publication date: March 6, 2025Inventors: Hung-Li Chiang, Tsung-En Lee, Jer-Fu Wang, Chao-Ching Cheng, Iuliana Radu, Cheng-Chi Chuang, Chih-Sheng Chang, Ching-Wei Tsai
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Publication number: 20250078878Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.Type: ApplicationFiled: November 19, 2024Publication date: March 6, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Sheng WANG, Kao-Cheng LIN, Yangsyu LIN, Yen-Huei CHEN, Cheng Hung LEE, Jonathan Tsung-Yung CHANG
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Publication number: 20250077780Abstract: A method for invoking a plugin of a large language model includes: acquiring natural language content; performing semantic understanding on the natural language content and detecting whether the natural language content hits a plugin to obtain a first plugin pointed to by the plugin hit result; comparing the first plugin with a second plugin corresponding to the current session understanding task to determine a to-be-executed session understanding task and a third plugin corresponding to the to-be-executed session understanding task; acquiring the language understanding content of the to-be-executed session understanding task and sending the language understanding content to the large language model to obtain the input parameter of the third plugin; and calling the third plugin according to the input parameter of the third plugin to obtain the calling result of the to-be-executed session understanding task.Type: ApplicationFiled: June 20, 2024Publication date: March 6, 2025Inventors: Yongkang Xie, Guming Gao, Penghao Zhao, Xue Xiong, Qian Wang, Dongze Xu, En Shi, Yuxuan Li, Sheng Zhou, Shupeng Li, Yao Wang, Zhou Xin
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Publication number: 20250079568Abstract: Disclosed is a fully immersed energy storage device, which includes a casing and a water pump. An insulation box is mounted inside the casing, and the insulation box is assembled with an assembly plate thereon. A mounting platform is mounted on the assembly plate and assembled with an annular rack. A rotating groove is provided between the mounting platform and the annular rack. Balls are placed in the rotating groove. The mounting platform is assembled with an assembly block, on which a rotating shaft is mounted. One end of the rotating shaft connects to a gear. The other end of the rotating shaft connects to a first assembly rod, to which a second assembly rod is connected. The second assembly rod connects to a fixed block, which is connected to an energy storage box. A motor base is mounted on the casing. A motor is mounted on the motor base.Type: ApplicationFiled: August 15, 2023Publication date: March 6, 2025Applicant: CSG PWR GEN (GUANGDONG) ENERGY STOR TECH CO., LTDInventors: Zhiqiang WANG, Chao DONG, Bangjin LIU, Sheng WAN, Jin WANG, Di XIAO, Jiasheng WU, Man CHEN, Yumin PENG, Yueli ZHOU, Cheng PENG, Min ZHANG, Bin WU, Linwei WANG, Qihua LIN, Xiaodong ZHENG, Zheng WENG, Shaohua ZHAO, Lunsen ZOU
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Publication number: 20250074767Abstract: A green hydrogen production system, a green power production system, a green hydrogen and green power production system, and methods of implementing the same are provided. Catalyst for hydrogen production is sent to a raw-material mixing unit, mixed with water, and then reacted in a first water splitting unit therein to generate hydrogen gas and oxidized catalyst for hydrogen production. The hydrogen gas is delivered to a hydrogen power generation unit to produce power while the oxidized catalyst for hydrogen production is sent to a photon-plasma decomposition unit for being reduced into the catalyst for hydrogen production and oxygen generated is sent to the hydrogen power generation unit to generate power. Thereby hydrogen, power, and raw materials used in the system are recycled during operation. Therefore, green hydrogen and green power with reasonable price obtained can replace fossil fuels to solve climate change and global warming issues.Type: ApplicationFiled: November 8, 2023Publication date: March 6, 2025Inventor: CHI-SHENG WANG
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Publication number: 20250076594Abstract: Optical devices and methods of manufacture are presented in which a multi-tier connector is utilized to transmit and receive optical signals to and from an optical device. In embodiments a multi-tier connection unit receives optical signals from outside of an optical device, wherein the optical signals are originally in multiple levels. The multi-tier connection unit then routes the optical signals into a single level of optical components.Type: ApplicationFiled: December 18, 2023Publication date: March 6, 2025Inventors: Chen-Hua Yu, Tung-Liang Shao, Yi-Jan Lin, Yu-Sheng Huang, Tsung-Fu Tsai, Chao-Jen Wang, Szu-Wei Lu
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Patent number: 12242730Abstract: A data arrangement method based on file system, a memory storage device and a memory control circuit unit are disclosed. The method includes: analyzing a file system stored in a system region to obtain a plurality of first logical units to which a first file belongs and first distribution information of a plurality of first physical units in a storage region, wherein the first physical units are mapped by the first logical units; determining whether to activate a data arrangement operation on the first file according to the first distribution information; after the data arrangement operation on the first file is activated, reading first data belonging to the first file from the first physical units; and writing, sequentially, the read first data to at least one second physical unit in the storage region.Type: GrantFiled: March 24, 2023Date of Patent: March 4, 2025Assignee: Hefei Core Storage Electronic LimitedInventors: Chih-Ling Wang, Yin Ping Gao, Qi-Ao Zhu, Kuai Cao, Dong Sheng Rao
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Patent number: 12242506Abstract: A database system can configure network devices, such as a primary database in a multi-tenant deployment and a secondary database in a private deployment, to send and receive sequence messages, such as input data indicative of a selection of a link. The database system can create a secure share area in the private deployment in response to receiving the input data indicative of the selection of the link. The database system can replicate the data from the multi-tenant deployment to the secure share area in the private deployment and share the replicated data from the secure share area to the secondary database hosted in the private deployment.Type: GrantFiled: October 31, 2023Date of Patent: March 4, 2025Assignee: Snowflake Inc.Inventors: Pui Kei Johnston Chu, Benoit Dageville, Shreyas Narendra Desai, Khondokar Sami Iqram, Subramanian Muralidhar, Chieh-Sheng Wang, Di Wu
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Patent number: 12243930Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.Type: GrantFiled: July 27, 2022Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Tai Chang, Tung-Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
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Patent number: 12243837Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.Type: GrantFiled: August 7, 2023Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
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Patent number: 12243907Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.Type: GrantFiled: January 5, 2024Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
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Publication number: 20250072058Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a substrate, complex two-dimensional material layers disposed over the substrate, a gate structure and source and drain regions. The complex two-dimensional material layers are arranged spaced apart from one each other and in parallel to one another. The gate structure is disposed across and wraps around and surrounds first portions of the complex two-dimensional material layers. The source and drain regions are disposed on opposite sides of the gate structure and wrap around and surround second portions of the complex two-dimensional material layers.Type: ApplicationFiled: August 21, 2023Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jer-Fu Wang, Hung-Li Chiang, Goutham Arutchelvan, Wei-Sheng Yun, Chao-Ching Cheng, Iuliana Radu
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Patent number: 12234569Abstract: A fabricating method of a non-enzyme sensor element includes a printing step, a coating step and an electroplating step. In the printing step, a conductive material is printed on a surface of a substrate to form a working electrode, a reference electrode and an auxiliary electrode, and a porous carbon material is printed on the working electrode to form a porous carbon layer. In the coating step, a graphene film material is coated on the porous carbon layer of the working electrode to form a graphene layer. In the electroplating step, a metal is electroplated on the graphene layer by a pulse constant current to form a catalyst layer including a metal oxide.Type: GrantFiled: February 7, 2022Date of Patent: February 25, 2025Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Hsiang-Yu Wang, Yi-Yu Chen, Shih-Hao Lin, Yu-Sheng Lin
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Patent number: 12235886Abstract: An embodiment includes executing a querying process that returns database documents containing text associated with a database environment. The embodiment tokenizes the database documents into a series of n-gram tokens and groups the tokens into topic classes using natural language processing (NLP). The embodiment also generates a feature map by applying a convolution layer to an image that depicts a database structure graph of the database environment. The embodiment detects an architectural element in the image by applying a region proposal network (RPN) to the feature map and classifies the architectural element into one of the plurality of topic classes using a trained neural network. The embodiment renders, responsive to a user selection of the architectural element, an overlay depicting information about the architectural element using text and other architectural elements that are in a same topic class as the user-selected architectural element.Type: GrantFiled: January 10, 2022Date of Patent: February 25, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sheng Yan Sun, Shuo Li, Xiaobo Wang, Hong Mei Zhang
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Patent number: 12235972Abstract: The disclosure provides a security analysis method and system based on protocol state, which relates to the technical field of protocol security protection. The method includes the following: a node traversal table is built, the node traversal table is scanned and analyzed according to the protocol trigger sequence rule, a first security evaluation factor of a protocol stack is determined, and a second security evaluation factor of each protocol is determined based on protocol normal application rule, and the trustworthiness degree of the second security factor is determined based on the first security factor, and the second security factor is revised based on the trustworthiness degree, and the security state of the protocol is determined according to the revised second security factor, thus the analysis of the protocol state is realized, and the security of the protocol can be accurately determined.Type: GrantFiled: July 9, 2024Date of Patent: February 25, 2025Assignee: HUANENG INFORMATION TECHNOLOGY CO., LTD.Inventors: Ziqiang Wen, Hongjian Qi, Shuo Han, Chenghua Qu, Yufei Wang, Lei Xu, Zhongying Pan, Sheng Ye, Shouhui Xin, Wei Li, Yujie Liu, Qiang Zhang, Chengfeng Song, Hongwei Zhang, Yanfei Xu, Xushuai Qin, Xunan Deng
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Publication number: 20250061346Abstract: A method of determining interaction information, an electronic device and a storage medium are provided, which relates to a field of artificial intelligence technology, in particular to a large model, a generative model, an NLP, an intelligent search and other fields. An implementation is to determine a plurality of questioning dimensions according to query information of a subject and historical query information, where each questioning dimension includes a dimension name and a plurality of options; determine a target questioning dimension from the plurality of questioning dimensions according to evaluation values of the plurality of questioning dimensions and whether semantic information of the plurality of questioning dimensions are consistent with semantic information of a query result associated with the query information; and determine the interaction information according to the dimension name and the plurality of options in the target questioning dimension.Type: ApplicationFiled: October 31, 2024Publication date: February 20, 2025Applicant: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.Inventors: Xiao LI, Xin JIA, Simiu GU, Junfeng WANG, Haibo SHI, Yu LU, Sheng XU, Liang ZHANG, Wenjie ZHOU, Yijun LIU, Mei LU, Zichen WU, Min YANG, Huanjie WANG, Qiao TANG, Mengmeng CUI
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Publication number: 20250054283Abstract: The present invention provides a training system and method, a testing system and method, a data filtering system and method, and a computer readable recording medium with stored program that includes verifying whether an object detection model has completed a training set learning and determining whether the object detection model is overfitting with a validation set, and outputting the training model as a master model before the object detection model is overfitting, and how to iterate the master model to match the test set test results and continuously maintain an online test level. The present invention provides a standardized method for achieving data marking consistency and training data selection.Type: ApplicationFiled: November 21, 2023Publication date: February 13, 2025Inventors: Tsai-Sheng SHEN, Yu-Yu SHIH, Kuang-Yu WANG
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Patent number: D1063805Type: GrantFiled: September 28, 2023Date of Patent: February 25, 2025Assignee: SHANDONG LINGLONG TIRE CO., LTDInventors: Feng Wang, Tian Yang, Zheng Wang, Xuehua Zang, Sheng Yang