Patents by Inventor Sheng Wang
Sheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978664Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.Type: GrantFiled: July 29, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
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Patent number: 11976429Abstract: The present invention discloses a shed tunnel structure for preventing a falling rock, including a shed tunnel body and a buffer plate for bearing impact of the falling rock, where the shed tunnel body includes a first supporting structure, and the first supporting structure is arranged on a side away from a ramp; one end of the buffer plate is connected to the ramp; a side face of the buffer plate close to the shed tunnel body is in movable contact with the first supporting structure, and the contact position is close to the other end of the buffer plate. The objective of resisting continuous impact of the falling rock can be achieved through the structural design.Type: GrantFiled: May 2, 2022Date of Patent: May 7, 2024Assignee: Sichuan Communication Surveying & Design Institute Co., Ltd.Inventors: Song Yuan, Xibao Wang, Liangpu Li, Peiyuan Liao, Sheng Zhang, Zhengzheng Wang, Zhixiang Yu, Tingbiao Zhang, Guoqiang Zheng, Junbing Li, Yafeng Jin, Weijin Zhou, Lisong Gan, Ke Zhou, Jicheng Wei, Daquan Zhao
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Publication number: 20240143005Abstract: A power supply suppression circuit (10), a chip and a communication terminal that only achieve the enhancement of the power supply suppression capability from an AC, without generating additional circuit power consumption. The power supply suppression circuit (10) comprises a sampling unit (105), a compensation unit (106), and an amplification unit (107). The sampling unit (105) is connected to the compensation unit (106), and the compensation unit (106) is connected to the amplification unit (107). The power supply suppression circuit (10) obtains an AC signal from a preset sampling node position of a low dropout regulator, and generates an enhancement signal in phase with the AC signal on a power supply (Vdd) on the basis of the AC signal, such that the input end voltage of the power output stage of the low dropout regulator immediately follows the voltage change of the power supply (Vdd).Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Applicant: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.Inventors: Chunling LI, Yongshou WANG, Cheng CHEN, Sheng LIN
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Publication number: 20240145494Abstract: An image sensor structure including a substrate, a first pixel structure, a second pixel structure, a dielectric layer, and a conductive layer stack is provided. The first pixel structure includes a first light sensing device. The second pixel structure includes a second light sensing device. The conductive layer stack includes conductive layers. The conductive layer stack has a first opening and a second opening. The first opening is located directly above the first light sensing device and passes through the conductive layers. The second opening is located directly above the second light sensing device and passes through the conductive layers. The second minimum width of the second opening is smaller than the first minimum width of the first opening. The luminous flux of the second pixel structure is different from the luminous flux of the first pixel structure.Type: ApplicationFiled: November 22, 2022Publication date: May 2, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ju-Sheng Lu, Yi-Ting Wang, Ming-Chan Liu
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Publication number: 20240145498Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.Type: ApplicationFiled: January 4, 2023Publication date: May 2, 2024Inventors: Hao-Lin Yang, Fu-Sheng Kuo, Ching-Chun Wang, Hsiao-Hui Tseng, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240142677Abstract: A notched filter includes a multilayer having alternating first and second polymer layers, the first polymer layers each including an isotropic polymer thin film having in-plane refractive indices n1x and n1y, and the second polymer layers each including an isotropic or anisotropic polymer thin film having in-plane refractive indices n2x and n2y, where a thickness of each successive first polymer layer decreases with increasing distance from a centerline of the multilayer, and a thickness of each successive second polymer layer increases with increasing distance from the centerline. Such a filter may be configured to reflect incident light having a desired polarization state within a predetermined and relatively narrow band.Type: ApplicationFiled: October 9, 2023Publication date: May 2, 2024Inventors: Zhaoyu Nie, Sheng Ye, Liliana Ruiz Diaz, Weihua Gao, Spencer Allan Wells, Andrew John Ouderkirk, Arman Boromand, Junren Wang, Tingling Rao, Lafe Joseph Purvis, II, Hend Baza
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Publication number: 20240145569Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia YEO, Sung-Li WANG, Chi On CHUI, Jyh-Cherng SHEU, Hung-Li CHIANG, I-Sheng CHEN
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Publication number: 20240146801Abstract: Embodiments of this application provide a peer-to-peer network transmission method, applied to a first peer node in the peer-to-peer network. The transmission method includes obtaining a target public network IP address and a target public network port of a second peer node from a networking service center, wherein the second peer node is located in the peer-to-peer network and configured to access a public network through a corresponding NAT device, and wherein public network IP addresses and public network ports of all nodes in the peer-to-peer network are collected by the networking service center in advance; and establishing a connection with the second peer node based on the target public network IP address and the target public network port to perform NAT traversal transmission.Type: ApplicationFiled: January 19, 2022Publication date: May 2, 2024Inventor: Sheng WANG
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Patent number: 11969286Abstract: A system for visualization and quantification of ultrasound imaging data according to embodiments of the present disclosure may include a display unit, and a processor communicatively coupled to the display unit and to an ultrasound imaging apparatus for generating an image from ultrasound data representative of a bodily structure and fluid flowing within the bodily structure. The processor may be configured to estimate axial and lateral velocity components of the fluid flowing within the bodily structure, determine a plurality of flow directions within the image based on the axial and lateral velocity components, differentially encode the flow directions based on flow direction angle to generate a flow direction map, and cause the display unit to concurrently display the image including the bodily structure overlaid with the flow direction map.Type: GrantFiled: November 22, 2022Date of Patent: April 30, 2024Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Hua Xie, Shiying Wang, Sheng-Wen Huang, Francois Guy Gerard Marie Vignon, Keith William Johnson, Liang Zhang, David Hope Simpson
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Publication number: 20240136346Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.Type: ApplicationFiled: April 17, 2023Publication date: April 25, 2024Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
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Publication number: 20240131808Abstract: A tape laying device includes a tape transmission mechanism, a compaction head mechanism, a cutter mechanism, a heating mechanism and a motion mechanism. The tape transmission mechanism is configured to transmit the pre-impregnated tape. The compaction head mechanism, connected with the tape transmission mechanism, is configured to depress and drive the pre-impregnated tape transmitted by the tape transmission mechanism to follow a moving path so as to adhere the pre-impregnated tape onto the mould surface. The cutter mechanism is configured to cut the pre-impregnated tape. The heating mechanism, disposed downstream to the cutter mechanism, is configured to heat the pre-impregnated tape. The motion mechanism is used to have the cutter mechanism having an active path to move toward the moving path while the cutter mechanism cuts the pre-impregnated tape.Type: ApplicationFiled: December 7, 2022Publication date: April 25, 2024Inventors: TENG-YEN WANG, SHUN-SHENG KO, MIAO-CHANG WU, TUNG-YING LIN, CHAO-HONG HSU
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Publication number: 20240136387Abstract: An image sensor structure and a method of fabricating the structure are disclosed, in image sensor structure, at least one die is bonded to pixel substrate by bonding first bonding layer to second bonding layer, and the die includes signal processing circuit and/or storage device for photosensitive elements in pixel substrate. The die is bonded to the pixel substrate so that the signal processing circuit and/or storage device is/are coupled to photosensitive elements in pixel substrate. In this way, signal processing and/or storage functions of the image sensor can be provided without additional occupation of the area of the pixel substrate, allowing for more photosensitive elements to be arranged on the pixel substrate with the same area and thus resulting in a larger photosensitive area. Moreover, less wiring is needed on the 2D plane of the pixel substrate, helping in reducing interference with signals and delays and improving imaging quality.Type: ApplicationFiled: December 23, 2022Publication date: April 25, 2024Inventors: Guoliang YE, Shengjin SONG, Sheng HU, Ying WANG
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Publication number: 20240134538Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.Type: ApplicationFiled: June 5, 2023Publication date: April 25, 2024Inventors: Po-Sheng CHOU, Hsiang-Yu HUANG, Yan-Wen WANG
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Patent number: 11965959Abstract: The present disclosure describes ultrasound systems configured to enhance flow imaging and analysis by adaptively adjusting one or more imaging parameters in response to acquired flow measurements. Example systems can include an ultrasound transducer and one or more processors. Using the system components, mean flow velocity magnitude and acceleration can be determined within a target region during an acquisition phase, which may include a cardiac cycle. One or more adjusted flow imaging parameters, such as adjusted ensemble length, temporal smoothing filter length and/or step size, can be determined based on the acquired flow measurements to increase the signal quality of newly acquired ultrasound echo signals. The adjusted flow imaging parameters can then be applied by the ultrasound transducer during a second acquisition phase.Type: GrantFiled: October 14, 2019Date of Patent: April 23, 2024Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Shiying Wang, Sheng-Wen Huang, Hua Xie, Keith William Johnson, Liang Zhang, Thanasis Loupas, Truong Huy Nguyen
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Patent number: 11966338Abstract: This disclosure provides a method, a computing system, and a computer program product for managing prefetching of pages in a database system. The method comprises obtaining shared information associated with page access, wherein the shared information associated with the page access includes information associated with the page access from a plurality of computing nodes. The method further comprises determining whether to prefetch a number of pages into a global buffer pool based at least on the shared information associated with the page access using a sequential prefetching method.Type: GrantFiled: July 19, 2022Date of Patent: April 23, 2024Assignee: International Business Machines CorporationInventors: Sheng Yan Sun, Xiaobo Wang, Shuo Li, Chun Lei Xu
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Publication number: 20240130038Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.Type: ApplicationFiled: November 23, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Chin-Hsun WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Hung, Wei-Yu Liao, Chi-Min Chang
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Publication number: 20240129450Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The display may have a number of independently controllable viewing zones. Each viewing zone displays a respective two-dimensional image. Each eye of the viewer may receive a different one of the two-dimensional images, resulting in a perceived three-dimensional image. The electronic device may include display pipeline circuitry that generates and processes content to be displayed on the lenticular display. Content generating circuitry may initially generate content that includes a plurality of two-dimensional images, each two-dimensional image corresponding to a respective viewing zone. Pre-processing circuitry may subsequently anisotropically resize each two-dimensional image. Pixel mapping circuitry may then be used to map the resized two-dimensional images to the array of pixels in the lenticular display.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: Sheng Zhang, Chaohao Wang, Yue Ma
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Publication number: 20240128626Abstract: A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.Type: ApplicationFiled: November 25, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Yu-Kuang WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
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Publication number: 20240124456Abstract: An aza-ergoline derivative and a preparation method therefor and an application thereof. The derivative has a structure as shown in formula (I). The aza-ergoline derivative has good affinity, agonistic activity or selectivity to a dopamine D2 receptor.Type: ApplicationFiled: January 29, 2022Publication date: April 18, 2024Inventors: Jianjun CHENG, Sheng WANG, Huan WANG, Luyu FAN, Zhangcheng CHEN, Jing YU, Jianzhong QI, Fen NIE
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Publication number: 20240127109Abstract: A federated learning method includes: providing importance parameters and performance parameters by client devices respectively to a central device, performing a training procedure by the central device, wherein the training procedure includes: selecting target devices from the client devices according to a priority order associated with the importance parameters, dividing the target devices into training groups according to a similarity of the performance parameters, notifying the target devices to perform iterations according to the training groups respectively to generate trained models, transmitting the trained models to the central device, and updating a global model based on the trained models, performing the training procedure again or outputting the global model to the client devices based on a convergence value of the global model and the number of times of performing the training procedure.Type: ApplicationFiled: November 10, 2022Publication date: April 18, 2024Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Ping Feng WANG, Chiun Sheng HSU, Chi-Yuan CHOU, Fu-Chiang CHANG