Abstract: A distributed data processing system and a distributed data processing method are provided. The distributed data processing system includes a computing device and at least one additional computing device.

Abstract: Systems and methods are described for selecting models to perform monocular depth estimation. A computing device may receive a plurality of image and select an image from the plurality of images to evaluate a first machine-learning model and a plurality of machine-learning models are smaller than the first machine-learning model. The computing device may process the image using a first machine-learning model to generate a first predicted result. The computing device may also process the image using the plurality of machine-learning models to generate at least a second predicted result and a third test data set. The computing device may select a second machine-learning model from the plurality of machine-learning models based on a comparison of the first predicted result with the at least the second predicted result and the third test data set. The computing device may then process the plurality of images using the second machine-learning model.

Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad.

Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.

Abstract: A grating regulating device is applied to a 3D displaying device. The 3D displaying device includes a display panel, the display panel includes a first polarizing unit, the grating regulating device is provided on one side of the display panel away from the first polarizing unit, and the grating regulating device includes: a first substrate and a second substrate, wherein the first substrate and the second substrate face each other; a second polarizing unit provided on one side of the second substrate away from the first substrate; and a third polarizing unit provided on one side of the first substrate away from the second substrate; and an absorption axis of the first polarizing unit and an absorption axis of the second polarizing unit are perpendicular, and the absorption axis of the second polarizing unit and an absorption axis of the third polarizing unit are perpendicular.

Abstract: A method for assessing a channel quality and a network system are provided. The network system includes a network device and a plurality of mobile stations. The network device and the mobile stations wirelessly communicate with each other through a plurality of channels. The method includes the following steps: configuring the network device to divide the channels into a plurality of channel groups according to the corresponding mobile stations; configuring the network device to send at least one packet through each of the channel groups to the corresponding mobile station for channel measurement, so as to obtain a plurality of quality parameters respectively for the channels; and configuring the mobile stations to transmit the quality parameters back to the network device, and configuring the network device to assess a communication quality of the channels based on the received quality parameters.

Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: Disclosed in the present invention are a thiophene ring compound, a preparation method therefor and an application thereof. The structure of the thiophene ring compound of the present invention is as shown in formula I. The compound of the present invention has good affinity and agonistic activity against at least one of a dopamine receptor and a 5-hydroxytryptamine receptor.

Abstract: Embodiments of the present application provide a rotor and a motor. The rotor has a plurality of through-hole groups. Each through-hole group has a plurality of through-holes distributed in a radial direction. The rotor also has auxiliary holes. Each auxiliary hole is located between every two radially adjacent through-holes. A sectional area of each auxiliary hole is less than a sectional area of each through-hole. When a first angle, a second angle and a third angle are defined between three portions of each auxiliary hole and the q-axis respectively, the third angle is greater than or equal to the first angle, and the third angle is less than or equal to the second angle.

Abstract: A method of adaptively controlling a brushless DC motor includes steps of: controlling the brushless DC motor rotating at a first speed according to an operation curve, accumulating a running time of the brushless DC motor, estimating a remaining used time of a bearing of the brushless DC motor according to the accumulated running time, executing an alarm operation when the remaining used time is less than a predetermined time, and decreasing the speed of the brushless DC motor to run at a second speed to prolong the used time of the bearing.

Abstract: A co-packaged structure for optics and electrics includes a substrate, an optical module and an electrical connection layer. The optical module includes a carrier and an optical transceiver unit. The carrier is mounted on the substrate. The optical module is mounted on the carrier. The electrical connection layer is mounted on the substrate, and the carrier is electrically connected with a circuitry on the substrate through the electrical connection layer. A plurality of fiber accommodation through hole are formed on the substrate and correspond to the optical transceiver unit.

Abstract: A round wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core itself is a silver-based wire core, wherein the coating layer is a double-layer comprised of a 1 to 100 nm thick inner layer of palladium or nickel and an adjacent 1 to 250 nm thick outer layer of gold, wherein the outer layer of gold exhibits at least one of the following intrinsic properties A1) and A2): A1) the average grain size of the crystal grains in the outer layer of gold, measured in longitudinal direction, is in the range of 0.1 to 0.8 ?m; A2) 60 to 100% of the crystal grains in the outer layer of gold are oriented in <100> direction, and 0 to 20% of the crystal grains in the outer layer of gold are oriented in <111> direction.

Abstract: Various embodiments provide for replicating a share across deployments of a data platform, where the share can be on a source deployment and the share can be replicated on one or more target deployments, and where the share is replicated with one or more database objects of the source deployment associated with the share. Some embodiments analyze the share to be replicated and, based on the analysis, determine one or more database objects that would be replicated to the one or more target deployments to enable a replica of the share on the one or more target deployments.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.

Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.

Abstract: Disclosed are non-transitory computer-readable media, systems, and computer-implemented methods that describe obtaining hot spot (HS) location information with respect to a printed pattern; obtaining LFP search criteria for searching the printed pattern to determine a local focus point (LFP) for an imaging device; selecting a HS area in the printed pattern that contains a HS; and determining the LFP proximate to the HS area based on the LFP search criteria, the LFP not containing the HS.

Abstract: A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.

Abstract: A multilevel-cache-based data processing method is provided, which is applied to a server computing device. The server computing device includes a first-level cache and a second-level cache. The first-level cache includes a plurality of first-type storage nodes. The second-level cache includes a plurality of second-type storage nodes. The data processing method includes identifying a target node based on a current hash ring in response to receiving a read request; determining whether the target node is any one of the plurality of first-type storage nodes; and in response to determining that the target node is not any one of the plurality of first-type storage nodes, reading response data from the plurality of second-type storage nodes for responding to the read request, and returning the response data. According to the method, a speed of responding to the read request can be increased, and pressure of the first-level cache can be reduced.