Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first nanostructure and a second nanostructure over a substrate, forming a first interfacial layer on the first nanostructure and a second interfacial layer on the second nanostructure, forming a first gate dielectric layer on the first interfacial layer and a second gate dielectric layer on the second interfacial layer, forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer, and driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer.

Abstract: An electronic device includes a first metal layer, a first insulating layer disposed on the first metal layer, a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, a fourth metal layer, a fourth insulating layer and an electronic component. The second metal layer is disposed on the first insulating layer. The second insulating layer is disposed on the second metal layer. The third metal layer is disposed on the second insulating layer. The third insulating layer is disposed on the third metal layer. The fourth metal layer is disposed on the third insulating layer. The fourth insulating layer is disposed on the fourth metal layer. The electronic component is disposed on the fourth insulating layer and electrically connected to the fourth metal layer. A Young's modulus of the third insulating layer is less than a Young's modulus of the first insulating layer.

Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

Abstract: A computing device collects a plurality of data samples. Each data sample represents a signal activity of a plurality of signals of the chip. The computing device selects a subset of signals from the plurality of signals as proxies. These proxies are correlated with an actual power consumption of the chip according to a criterion. The computing device trains the power model using signal activities of the plurality of signals as inputs and the actual power consumption as an output. The computing device fine-tunes coefficients of the proxies in the power model. This fine-tuning adjusts an estimation error between an estimated power consumption output by the power model and the actual power consumption.

Abstract: A sofa with adjustable coupled headrest and backrest includes a base movably connected with a side panel and a coupling sheet for backrest hinged at the side panel, and a backrest assembly including a connection element of backrest with a front end hinged at a rear end of the side panel at an upper positionn and a connection rod of backrest with an upper end hinged at a rear end of the connection element of backrest, and with a lower end hinged at the coupling sheet for backrest, the base is provided with a drive member to switch a backrest frame to a lying position, and a coupling assembly for headrest configured to force the connection element for headrest to flip relative to a backrest skeleton is provided between the connection rod of backrest and the connection element for headrest.

Abstract: The present invention discloses a set of novel epigenetic biomarkers for early prediction, treatment response, recurrence and prognosis monitoring of a breast cancer. Aberrant methylation of the genes can be detected in tumor tissues and plasma samples from breast cancer patients but not in normal healthy individual. The present disclosure also discloses primers and probes used herein.

Abstract: A system produces a dolly zoom effect by utilizing side view information. The system first captures a main image at a main location. The main image includes at least a foreground object of a given size and a background. The system calculates one or more side view locations based on a zoom-in factor to be applied to the background and an estimated size of the foreground object. The system then guides a user to capture one or more side view images at the one or more side view locations. The foreground object of the given size is superimposed onto a zoomed-in background. Then the side view information is used by the system to perform image inpainting.

Abstract: A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.

Abstract: An optical lens assembly includes, in order from an object side to an image side: a first lens with negative refractive power; a second lens with negative refractive power; a third lens with positive refractive power; a fourth lens with positive refractive power; a fifth lens with negative refractive power; a sixth lens with positive refractive power; wherein a distance from an object-side surface of the first lens to an image plane along an optical axis is TL, an incident angle of a chief ray on the image plane at a maximum view angle of the optical lens assembly is CRA, a focal length of the optical lens assembly is f, and the following condition is satisfied: 51.73°<TL*CRA/f<129.65°.

Abstract: A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, at least one second build-up circuit layer, at least one conductive through hole, and a fine redistribution layer (RDL). The embedded block is fixed in a through cavity of the dielectric substrate. The electronic component is disposed in an opening of the embedded block. The first build-up circuit layer is disposed on a top surface of the dielectric substrate and electrically connected with the electronic component. The second build-up circuit layer is disposed on a bottom surface of the dielectric substrate and covers the embedded block. The conductive through hole is disposed in a via of the embedded block and electrically connects the first and the second build-up circuit layers. The fine RDL is disposed on and electrically connected to the first build-up circuit layer.

Abstract: Disclosed are a dimmable panel (001) and a display device. The dimmable panel includes a first substrate (101) and a second substrate (102) that are arranged opposite each other; a first electrode (103) and a second electrode (104) that are insulated from each other and located between the first substrate (101) and the second substrate (102), where the first electrode (103) and the second electrode (104) are located in a dimmable area (AA), at least one of the first electrode (103) and the second electrode (104) includes a plurality of strip-shaped electrodes, extension trends of all the strip-shaped electrodes are approximately the same, and orthographic projections of the strip-shaped electrodes on the first substrate (101) do not overlap each other; and a liquid crystal layer (105) located between the first substrate (101) and the second substrate (102), where the liquid crystal layer (105) is located in the dimmable area (AA).

Abstract: A process of characterizing a process window of a patterning process, the process including: obtaining a set of inspection locations for a pattern, the pattern defining features to be applied to a substrate with a patterning process, the set of inspection locations corresponding to a set of the features, the set of features being selected from among the features according to sensitivity of the respective features to variation in one or more process characteristics of the patterning process; patterning one or more substrates under varying process characteristics of the patterning process; and determining, for each of the variations in the process characteristics, whether at least some of the set of features yielded unacceptable patterned structures on the one or more substrates at corresponding inspection locations.

Abstract: A microphone stand structure includes a stand base, a frame set and a locking unit. The stand base includes a supporting rod, one end of the supporting rod includes a tapered groove and a first hole, the first hole penetrates the bottom of the tapered groove, and the inner wall of the tapered groove includes a first tooth part. A second hole penetrates a tapered convex part, a surface of the tapered convex part includes a second tooth part, the tapered convex part is fitted into the tapered groove, the second tooth part meshes with the first tooth part, and the second hole links to the first hole. The locking unit penetrates the first hole of the supporting rod and the second hole of the fastener.

Abstract: A dialogue system for cognitively impaired adults based on CST principles is provided. The dialogue system includes an encoder module, a decoder module, and an external knowledge module. The encoder module is configured to classify utterance and execute a progressive mask context training part and a text classification part. The progressive mask context training part performs a sentiment analysis function and a keyword extraction. The text classification part performs text classification tasks comprising emotion, strategy, and CST classifications. The decoder module is in electrical communication with the encoder module for response generation according to predicted values derived from attention weights in response to outcomes of the encoder module from the utterance.

Abstract: A method for secure data synchronization and sharing between distinct cloud environments is disclosed. The method involves establishing a trust relationship between a data provider's private cloud deployment and a data consumer's public cloud deployment. Utilizing hardware processors, a cross-region group sharing token is generated and validated to facilitate secure communication and data traffic between the two cloud deployments. Upon validation, a firewall policy that previously restricted data exchange is disabled, allowing for the replication of a target database from the private cloud to a secure share area accessible by the public cloud deployment. The data consumer is then enabled to access and utilize the replicated database within this secure area. The method ensures consistent data management across both deployments by managing the synchronization of the replicated database with the data provider's original database, thereby maintaining data consistency and integrity.

Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.

Abstract: A display device and a driving method thereof are provided. The display device includes: a display panel; and at least two grating panels; the grating panel includes a dielectric layer and driving structures disposed on at least one side of the dielectric layer; the grating panel includes grating units, the grating unit includes at least two driving structures; the driving structure is configured to receive a driving signal and form an electric field under the action of the driving signal; the electric field is used for driving a corresponding position of the dielectric layer to transmit light or shield light so that the grating unit forms a light-transmitting unit and a light-shielding unit; the grating panels include a first grating panel and a second grating panel stacked on a same side or two opposite sides of the display panel; the grating units are arranged along a first direction.

Abstract: The present application discloses techniques for adjusting data storage. The techniques comprises receiving a request of accessing target content from a user; determining a content size of the target content, and querying a cache unit to identify a set of cache blocks storing the target content; determining a space hit ratio based on the content size and a storage capacity corresponding to the set of cache blocks; adjusting an initial block size of the cache unit based on the space hit ratio and a block size of a lower-level storage relative to the cache unit to obtain a new block size of the cache unit when the space hit ratio is less than a predetermined threshold; and configuring newly set up cache blocks for the cache unit based on the new block size.

Abstract: Techniques for processing data involve receiving an access request for a logical block used for storing data, the access request including a logical block address for the logical block. Such techniques further involve determining, if it is determined that the logical block address is in a used address space, an index entry corresponding to the logical block address from index entries, the index entry indicating arrangements of logical blocks on a corresponding pool stripe, wherein the pool stripe includes disk blocks from disks in a disk pool, and data blocks form at least one data stripe for a disk array. Such techniques further involve determining a target block corresponding to the logical block based on the index entry. Such techniques further involve processing the access request by using the target block. Accordingly, the processing speed of sequential I/O operations is improved, time is saved, and user experience is improved.

Abstract: Provided herein are designs of a linear time-of-flight (TOF) mass spectrometer that achieves a high mass resolving power (MRP) to ions independently having a mass-to-charge (m/z) ratio between 1,000 and 100,000. The TOF mass spectrometer comprises an ion source, a flight tube, and an ion detector, in which the ion source comprises a sample plate, an extraction plate disposed at a first distance (d1) away from the sample plate; an end plate disposed at a second distance (d2) away from the extraction plate; a first electric field (e1) present between the sample plate and the extraction plate; and a second electric field (e2) present between the extraction plate and the end plate; the flight tube having a length of d3 is disposed downstream and adjacent to the ion source; and the ion detector is disposed downstream and adjacent to the flight tube; and the linear TOF mass spectrometer satisfies the set of criteria I or II, in which the set of criteria I includes (1) d1/L<0.